Processor Core Hang Detection via Free-Running Clock
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Solution Overview
Problem
Conventional processor hang detection mechanisms are inconsistent in detecting core hangs, particularly in chip multiprocessors with varying core frequencies and voltages, leading to potential missed hang conditions.
Innovation Solution
A processor with a hang detection unit featuring a counter unit using a free-running clock independent of the core clock frequency, and a detector logic unit that dynamically adjusts the count value and timeout based on instruction execution states and completion times, disabling hang detection for known non-error conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional timer-based hang detection mechanism is used with a core clock source, then the detection mechanism is simple to implement, but it fails to consistently detect hangs in chip multiprocessors with varying core frequencies and voltages
Solution Approach 1:
The patent changes the clock source parameter from core clock to free-running clock, and dynamically adjusts the timeout threshold parameter based on instruction type and core state. This resolves the contradiction by making the detection mechanism reliable across varying frequencies while managing complexity through parameter adaptation rather than structural complexity.
Solution Approach 2:
The patent introduces dynamic adjustment of timeout thresholds based on instruction execution state, core frequency, and voltage conditions. The detection mechanism adapts its parameters in real-time rather than using fixed thresholds, achieving reliability across variable operating conditions without requiring overly complex detection logic.
2Measurement precision
If a fixed timeout threshold is used for hang detection, then the detection logic is simple, but it produces false positives for legitimate long-execution instructions and false negatives for variable-frequency cores
Solution Approach 1:
The timeout threshold is dynamically adjusted based on the specific instruction being executed, core frequency, and operational state. This dynamic approach improves measurement precision by adapting to varying execution times while avoiding false positives, without requiring excessively complex detection logic through systematic parameter adjustment.
Solution Approach 2:
Different timeout thresholds are applied to different instruction types and core states. Rather than using a single global threshold, the system tailors the detection parameters to local conditions (specific instruction characteristics and core operational state), improving accuracy while maintaining manageable logic complexity through localized parameter selection.
3Reliability
If hang detection is continuously monitored for all instructions, then all hangs are detected, but the detection mechanism generates false positives for known non-error conditions like intentional stalls
Solution Approach 1:
The system performs preliminary identification of instructions that are known to cause intentional stalls or long execution times before applying hang detection. By pre-characterizing instructions with expected long execution patterns, the system can exclude them from hang detection or apply different thresholds, maintaining reliable hang detection coverage while avoiding false positives from known benign conditions.
Solution Approach 2:
The detection mechanism incorporates feedback about core state and instruction characteristics to modulate detection behavior. When the system detects that a core is in a state known to produce false positives (such as intentional stalls), it adjusts or disables detection for that specific condition, maintaining overall detection reliability while filtering out false alarms through state-aware feedback control.
Data Source
AI summary
Mechanism for consistent core hang detection on a processor with multiple processor cores, each having one or more instruction execution pipelines. Each core may also include a hang detection unit with a counter unit that may generate a count value based on a clock source having a frequency that is independent of a frequency of a processor core clock. The hang detection unit may also include a detector logic unit that may determine whether a given instruction execution pipeline has ceased processing a given instruction based upon a state of the processor core and whether or not the given instruction has completed execution prior to the count value exceeding a predetermined value.