Processor Core Synchronization via Interrupt Controller
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Solution Overview
Problem
In computing systems with multiple processor cores, there is a need to synchronize processor cores efficiently during translation lookaside buffer (TLB) invalidation operations to ensure that all cores complete TLB instructions before proceeding, as existing methods can lead to performance degradation or deadlocks.
Innovation Solution
The implementation of an interrupt-based mechanism where an issuing processor core sends a data synchronization barrier (DSB)/GlobalSync interrupt to all receiving processor cores, ensuring that all TLB invalidation instructions are completed before resuming execution, using an interrupt controller to manage and acknowledge the completion of TLB operations without inserting external instructions into the pipeline.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processor cores use traditional synchronization methods for TLB invalidation, then synchronization can be achieved, but performance degrades and deadlocks may occur
Solution Approach 1:
The patent replaces traditional mechanical synchronization mechanisms (such as software barriers and memory fences) with an interrupt-based hardware mechanism. The interrupt controller generates interrupt messages that are delivered to receiving processor cores, allowing synchronization to be achieved through hardware-level interrupt handling rather than software-based mechanical synchronization, thereby improving both reliability and performance
Solution Approach 2:
The interrupt controller serves as an intermediary between the issuing processor core and the receiving processor cores. It manages the synchronization process by generating and distributing interrupt messages, coordinating the completion status, and enabling reliable communication without requiring direct core-to-core interaction, thus avoiding deadlocks and performance degradation
2Reliability
If external instructions are inserted into the pipeline to ensure synchronization, then synchronization is achieved, but pipeline efficiency decreases
Solution Approach 1:
The patent extracts the synchronization mechanism from the instruction pipeline by using interrupts. Instead of inserting synchronization instructions into the pipeline, the system uses interrupt messages delivered by the interrupt controller to coordinate synchronization between cores, thereby maintaining pipeline efficiency while ensuring synchronization reliability
Solution Approach 2:
The patent substitutes the mechanical approach of inserting external instructions into the pipeline with an interrupt-based mechanism. The interrupt controller handles synchronization coordination externally, allowing the pipeline to execute instructions efficiently without being interrupted by synchronization barriers, thus reducing pipeline complexity while maintaining synchronization assurance
Data Source
AI summary
Interrupt messages are sent from an interrupt controller to respective processor cores and data synchronization is managed among the processor cores. Each processor core includes a pipeline that includes a plurality of stages through which instructions of a program are executed, where stored order information indicates whether a state of the pipeline is in-order or out-of-order; and circuitry for receiving interrupt messages from the interrupt controller and performing an interrupt action in response to a corresponding interrupt message after ensuring that the order information indicates that the state of the pipeline is in-order when each interrupt action is performed. Managing the data synchronization includes generating a first interrupt message at an issuing processor core in response to a synchronization related instruction executed at the issuing processor core; and receiving the first interrupt message at each receiving processor core in a set of one or more receiving processor cores.