Processor Core Architecture for Flexible Large Number Processing
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Solution Overview
Problem
Current encryption processors face challenges in flexibility and cost-effectiveness, particularly when processing large numbers, as custom hardware processors are inflexible and costly, while general-purpose processors are inefficient for large number operations, leading to increased overhead and die area.
Innovation Solution
A processor with a single core that supports both large number processing operations and general-purpose microprocessor operations, combined with a programmable microcode memory for executing instructions, allowing for re-characterization of encryption processes to optimize efficiency without requiring additional cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If custom hardware processors are designed for encryption operations, then processing efficiency for large numbers is improved, but hardware costs and die area increase
Solution Approach 1:
The processor core is designed to perform both general-purpose operations and specialized large number processing operations through a unified architecture. The same core executes different instruction sets depending on the workload, eliminating the need for separate dedicated hardware processors for encryption while maintaining high processing efficiency through optimized instruction support for both domains.
2Productivity
If custom hardware processors are designed for encryption operations, then processing efficiency is improved, but device flexibility and upgradeability deteriorate
Solution Approach 1:
The processor employs dynamic instruction set extension capabilities where the instruction set can be modified and updated after the processor is manufactured. This allows the same hardware core to adapt to different encryption standards and large number processing requirements over time through software updates, providing both high processing efficiency and future-proof flexibility without requiring hardware redesign.
3Adaptability or versatility
If multiple processor cores are used to support different encryption processes, then adaptability is improved, but device complexity and die area increase
Solution Approach 1:
A single processor core is designed to execute multiple encryption processes and large number operations through instruction set variations rather than requiring multiple dedicated cores. The core can be configured to perform RSA, AES, and other cryptographic operations by executing different instruction sequences, reducing hardware complexity while maintaining high adaptability to various encryption standards.
4Ease of manufacture
If general-purpose processors are used for large number processing, then hardware costs are reduced, but processing efficiency deteriorates
Solution Approach 1:
The processor architecture segments the processing functionality by providing specialized instruction sets for large number operations within the general-purpose core. This allows the processor to maintain general-purpose versatility while incorporating optimized instruction paths for cryptographic operations, achieving both cost-effectiveness and high processing efficiency for large number arithmetic without requiring dedicated hardware.
Data Source
AI summary
A method of implementing large number multiplication and exponentiation is provided upon a general purpose microprocessor. These large number multiplication and exponentiation processes being common to cryptography standards such as RSA and AES that typically employ numbers with 512-bits, 1024-bits, and 2048-bits. According to the invention the method establishes the size of the large number processes according to value stored within a control register, this control register and other registers storing data are configured according to this value and accessed as N-bit registers (i.e. as 1024-bit registers for 1024-bit encryption. Additionally, the multiplication and exponentiation processes are handled according to the size of an arithmetic primitive, which is established according to the hardware configuration upon which the process is operating. As such the invention allows for an encryption process to adjust both to the configuration of the host microprocessor and supporting hardware/firmware and dynamically according to degree of security determined from the value stored within the control register.