Main Sub Processor Core Memory Synchronization
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Solution Overview
Problem
In computers with a calculation node that does not support precise exceptions, it is difficult to use memory mapped file functions and perform memory sharing between different processes, as the calculation node cannot recover from exceptions and maintain memory synchronization.
Innovation Solution
An information processing device with a main processor core and a sub processor core, where the main processor core has an operating system and synchronizes data in shared memory areas across both cores, even when the sub processor core is stopped, allowing for memory sharing and exception handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a calculation node uses a CPU that does not support precise exception, then device complexity is reduced and cost is lowered, but memory mapped file function cannot be used and memory sharing between processes becomes difficult
Solution Approach 1:
The patent introduces a control node as an intermediary between the calculation node and the memory mapped file system. The control node, which has precise exception handling capability, manages the memory mapping and file operations on behalf of the calculation node. This allows the calculation node to use memory mapped files without having precise exception support built into its CPU, as the control node handles the exception-prone operations.
Solution Approach 2:
The system is divided into two functional segments: a control node with full operating system and precise exception handling capability, and a calculation node with simplified CPU lacking precise exception support. By separating these functions, the calculation node can benefit from reduced complexity while the control node provides the necessary memory management services including memory mapped file support and inter-process memory sharing.
2Device complexity
If a calculation node stops on exception without precise exception support, then device complexity is reduced, but processing recovery becomes impossible and system reliability deteriorates
Solution Approach 1:
The control node acts as a mediator that intercepts and handles exceptions before they reach the calculation node's limited exception handler. When memory mapping or file operations trigger exceptions, the control node's operating system captures these exceptions, performs appropriate error handling, and ensures processing recovery, while the calculation node continues to operate with its simplified exception model.
Solution Approach 2:
The system prepares for potential exceptions by having the control node pre-establish exception handling mechanisms and memory management structures. The control node monitors and manages memory access patterns, preventing exceptions before they occur or immediately handling them when they do occur, thus cushioning the calculation node from the harmful effects of unhandled exceptions and ensuring continuous reliable operation.
Data Source
AI summary
A main processor core having a first memory and a sub processor core having a second memory and controlled by the main processor core are included. An operating system is incorporated in the main processor core, and no operating system is incorporated in the sub processor core. Shared memories are formed in the first and second memories, respectively. Data in the shared memories of the first and second memories are synchronized. The main processor core is configured to synchronize the data in the shared memories formed in the first and second memories while the sub processor core stops operating.