Processor Core Migration for Power Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Designing a processor that can meet the performance demands of high workloads while also supporting the lowest possible operating point for less demanding workloads is challenging, often resulting in unnecessary power consumption, especially in mobile systems.
Innovation Solution
An integrated circuit with multiple processor cores of different designs and performance levels, where each core can operate at specific voltage and frequency settings, allowing for automatic context switching between cores to optimize power usage based on workload demands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor is designed to operate at high operating points to meet performance demands, then performance is improved, but the minimum supply voltage must be increased which leads to unnecessary power consumption for less demanding workloads
Solution Approach 1:
The processor is divided into multiple operational modes or states, each with different performance characteristics and power consumption levels. The system segments the processing capability into high-performance mode (for demanding workloads) and low-power mode (for less demanding workloads), allowing selective activation based on actual needs rather than always operating at maximum capability.
Solution Approach 2:
The processor dynamically adjusts its operating point by transitioning between different states, changing its performance and power consumption characteristics in real-time based on workload demands. This dynamic adaptation allows the system to optimize the trade-off between performance and power consumption rather than being fixed at a single operating point.
2Power
If the minimum supply voltage is increased to support high operating points, then high-end performance is achieved, but power consumption increases for workloads that could run at lower voltages
Solution Approach 1:
The system changes the supply voltage parameter dynamically by transitioning between different operational states. Each state is associated with a specific voltage level and performance capability, allowing the system to match the voltage level to the actual workload requirements rather than maintaining a fixed high voltage level.
Solution Approach 2:
The processor is designed to perform multiple functions across different operational states, where each state provides a different combination of performance and power characteristics. This multi-functionality allows the same hardware to efficiently handle both high-performance demanding workloads and low-power less demanding workloads.
3Adaptability or versatility
If a processor supports multiple operating points with different voltage and frequency settings, then adaptability to different workloads is improved, but device complexity increases
Solution Approach 1:
The control mechanism is segmented into discrete states rather than being continuous, which simplifies the control logic. Each state represents a specific combination of voltage and frequency settings, making the system easier to manage and control compared to continuous adjustment mechanisms.
Data Source
AI summary
In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.