Processor Core Partition Registers for Interrupt Priority Blocking

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Solution Overview

Problem

Existing data processing systems face performance issues with interrupt priority blocking due to the location of interrupt priority blocking registers at the interrupt controller, leading to significant access time penalties and complexity in managing partitioned or virtualized machines.

Innovation Solution

Implementing a processor-based priority blocking mechanism using special purpose registers at the processor core to control interrupt priority blocking on a partition basis, allowing for independent management of interrupt blocking conditions for each partition without requiring software intervention at the interrupt controller.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If interrupt priority blocking registers are located at the interrupt controller, then interrupt blocking control is centralized, but access time increases and partition management complexity increases

Engineering Contradiction:

Improveaccess timeVSAvoidpartition management complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent divides the interrupt priority blocking mechanism into two parts: partition-based blocking registers at the processor core and interrupt controller-based blocking. This segmentation allows partition-specific blocking to be handled locally at the core, reducing access time for partition management while maintaining centralized interrupt controller control for overall interrupt handling.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces partition-based blocking registers at the processor core as an intermediary between the interrupt sources and the interrupt controller. These registers act as a local filtering mechanism that blocks interrupts based on partition affinity before they reach the interrupt controller, reducing the burden on the interrupt controller and improving access efficiency.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of operation

If interrupt priority blocking is managed on a per-processor core basis, then control is simplified, but partition-based blocking capability is lost

Engineering Contradiction:

Improvecontrol simplicityVSAvoidpartition-based blocking capability

Core Design Contradiction:

Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent implements partition-based blocking registers specifically at the processor core with affinity to particular partitions. This local quality allows the blocking mechanism to be tailored to specific partition requirements while maintaining the overall simplicity of the interrupt control system. Each partition can have its own blocking criteria without affecting other partitions.

Inventive Principle:

Principle #3Local quality

3Productivity

If software intervention is required at the interrupt controller for partition-based blocking, then centralized control is maintained, but software overhead increases

Engineering Contradiction:

Improvesoftware overheadVSAvoidinterrupt controller architecture

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent enables the processor core to autonomously handle partition-based interrupt blocking through hardware registers that automatically filter interrupts based on partition affinity. This self-service mechanism eliminates the need for software intervention at the interrupt controller for partition-based blocking, significantly reducing software overhead while maintaining centralized control capabilities when needed.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS9442870B2Interrupt priority management using partition-based priority blocking processor registers

Publication Date: 2016.09.13 EIREOG INNOVATIONS LTD

AI summary

A method and circuit for a data processing system (20) provide a processor-based partitioned priority blocking mechanism by storing priority levels and associated partition information in special purpose registers (27-29) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.