Processor Core Pipeline Switching for Energy Efficiency
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Solution Overview
Problem
Existing heterogeneous multicore systems face limitations in energy efficiency due to coarse-grained switching granularity and high overheads associated with migrating applications between cores, which restricts the ability to utilize more energy-efficient cores without sacrificing performance.
Innovation Solution
A processor core with two execution pipelines, where one is active and the other is inactive, and vice versa, sharing a fetch engine and architectural state to enable fine-grained switching between 'big' and 'little' execution modes, allowing the performance controller to dynamically adjust based on estimated cycles-per-instruction rates and performance metrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If application migration between heterogeneous cores is implemented, then energy consumption is reduced, but migration overhead limits switching granularity to tens or hundreds of millions of instructions
Solution Approach 1:
The patent merges the big.LITTLE core concepts into a single processor core by providing a first execution pipeline (big mode) and a second execution pipeline (LITTLE mode) within the same core, sharing common components such as the fetch engine, decode stage, and architectural state. This integration eliminates the need for explicit context transfer between separate cores, enabling fine-grained switching without migration overhead.
Solution Approach 2:
The processor core is segmented into multiple execution pipelines (big and LITTLE modes) that can be independently activated. The performance controller divides the execution time into quanta and selectively activates either the first or second execution pipeline based on performance requirements, allowing fine-grained control of energy consumption without sacrificing performance.
2Use of energy by moving object
If fine-grained switching between execution modes is enabled, then energy efficiency improves, but switching overhead must be minimized
Solution Approach 1:
Both execution pipelines share common hardware resources including the fetch engine, decode stage, L1 instruction cache, and architectural state (register file). This sharing eliminates the need for separate context storage and transfer mechanisms, reducing switching overhead to minimal pipeline flushing operations while enabling frequent mode transitions for fine-grained energy management.
Solution Approach 2:
The processor dynamically activates or deactivates the second execution pipeline based on real-time performance requirements. The performance controller monitors application characteristics and adjusts pipeline activation at the quantum level, allowing the system to adaptively optimize energy efficiency without fixed switching granularity constraints.
3Loss of time
If a single core provides both big and LITTLE execution modes, then migration overhead is eliminated, but core complexity increases
Solution Approach 1:
The single processor core is designed with multi-functionality by incorporating both big and LITTLE execution pipelines that share common resources. The fetch engine, decode stage, and architectural state serve both execution modes, allowing the core to function as either high-performance or energy-efficient mode as needed, reducing overall system complexity compared to separate heterogeneous cores.
Solution Approach 2:
Different parts of the processor are given different qualities: the first execution pipeline is optimized for high performance with wider issue width and more execution ports, while the second execution pipeline is optimized for energy efficiency with narrower issue width. The shared components provide common functionality, while the pipeline-specific components provide localized optimization for their respective modes.
Data Source
AI summary
A processor core includes a front end, and first and second back ends, the front end including a fetch engine configured to retrieve the sequence of data processing instructions for both the first back end and the second back end from a memory, and the first and second back ends are each configured to execute the sequence of program instructions. The core operates in a first mode in which the first back end is active and receives the sequence of data processing instructions from the fetch engine and the second back end is inactive, and a second mode in which the first back end is inactive and the second back end is active and receives the sequence of data processing instructions from the fetch engine, where the cycles-per-instruction rate is lower and energy consumption is higher for the first mode than the second mode.