Dynamic Processor Core Control for Thermal and Power Reduction
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Solution Overview
Problem
Computing devices face challenges in reducing thermal and power costs due to the static power leakage of processor cores in sleep states, which affects battery life and thermal management, especially when multiple cores are kept online unnecessarily.
Innovation Solution
A method is implemented to dynamically track the load of processor cores, designating busy cores based on load thresholds and maintaining only N+M cores online, where N is the number of busy cores and M is adjustable to account for additional threads, thereby minimizing the number of online cores and reducing static power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processor cores are kept online to handle processing tasks, then processing capability and productivity are improved, but static power consumption and thermal effects increase
Solution Approach 1:
The system dynamically adjusts the number of online processor cores based on real-time load conditions. The core controller continuously monitors processing loads and dynamically brings cores online or takes them offline, transforming the static core availability into a dynamic state that adapts to workload demands, thereby reducing unnecessary power consumption while maintaining processing capability.
Solution Approach 2:
The system changes the operational state parameter of processor cores from a fixed online state to a variable state based on load thresholds. By monitoring load percentages and comparing them against upper and lower thresholds, the system changes the state parameter (online/offline) of cores to optimize the balance between processing capability and power consumption.
2Use of energy by stationary object
If processor cores are placed in sleep states to reduce power consumption, then static power cost is reduced, but thermal management and battery life are adversely affected due to leakage
Solution Approach 1:
The invention extracts unnecessary processor cores from the online state and transitions them to offline state, removing their contribution to both power consumption and thermal effects. The core controller identifies cores with load below the lower threshold and takes them offline, effectively removing their static power consumption and associated thermal leakage from the system.
3Use of energy by stationary object
If the number of online cores is reduced to minimize power consumption, then energy efficiency is improved, but processing capacity may be insufficient for handling multiple threads
Solution Approach 1:
The system implements feedback control by continuously monitoring the processing loads on online cores and using this information to make decisions about bringing additional cores online or keeping existing cores active. The core controller receives feedback about thread counts and load distribution, and adjusts the number of online cores accordingly to maintain sufficient processing capacity while minimizing power consumption.
Solution Approach 2:
The system performs preliminary actions by maintaining a pool of offline cores that can be quickly brought online when needed. Rather than keeping all cores online continuously, the system prepares offline cores in advance that can be activated rapidly in response to increased workload demands, ensuring processing capacity is available when required without the continuous power cost of keeping all cores online.
Data Source
AI summary
Systems and methods for controlling processor cores on a computing device are disclosed. One method includes tracking a load of each of a plurality of processor cores and determining a load percentage of each of the processor cores. A core is designated as a busy core if a load percentage of the core exceeds an upper threshold, and the busy core designation is removed if the load percentage of the core drops below a lower threshold. To reduce power consumption and adverse thermal effects, no more than N+M cores are maintained online wherein N is a number of busy cores and M is generally zero, but may be increased to at least one.