Processor Core Self-Testing via Dedicated Hardware Controller
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Solution Overview
Problem
Existing self-testing methods for processor cores face challenges in achieving high fault grading capabilities while minimizing disruption to data processing and requiring extensive, complex software, especially in complex contemporary processor cores, where a balance is needed between frequent self-testing and system disruption.
Innovation Solution
The implementation of a self-test controller as a hardware monitor that administers self-testing externally to the processor core, using self-test support circuitry to directly export self-test data items to the control circuitry, allowing for fast context switching between data processing and self-testing without rebooting the processor core, and providing an independent path for self-test data export, independent of the memory interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If software-based self-testing is used, then area and power consumption are reduced, but the self-test software becomes extensive and complex
Solution Approach 1:
The patent divides the self-testing function into separate hardware components: a dedicated self-test controller and support circuitry integrated into the processor core. This segmentation transfers the complexity from software to dedicated hardware modules, reducing the burden on the main processor and eliminating the need for extensive self-test software while maintaining comprehensive fault detection capabilities.
Solution Approach 2:
The patent introduces a dedicated self-test controller as an intermediary component that manages the self-testing process. This controller works in conjunction with support circuitry embedded in the processor core to perform automated fault detection, eliminating the need for complex software-based self-testing while reducing area and power consumption compared to dual-core lock-step approaches.
2Reliability
If self-test software is frequently executed, then faults are quickly identified, but disruption to data processing increases
Solution Approach 1:
The patent enables continuous self-testing by integrating support circuitry directly into the processor core that can operate concurrently with or quickly transition from data processing. The dedicated self-test controller can initiate and manage self-test sequences without requiring system shutdown or extended interruption, allowing frequent fault detection while minimizing disruption to productive operations.
Solution Approach 2:
The processor core performs self-testing through dedicated support circuitry and a self-test controller that autonomously manage the testing process. This self-service capability allows the processor to quickly execute self-test sequences and return to data processing without requiring external intervention or prolonged interruption, thereby maintaining high productivity while achieving rapid fault identification.
3Reliability
If dual-core lock-step approach is used, then fault grading capability exceeds 90%, but area and power consumption increase
Solution Approach 1:
The patent extracts the essential self-testing functionality from a full dual-core lock-step implementation and implements it through a dedicated self-test controller and integrated support circuitry. This extraction maintains the high fault grading capability (exceeding 90%) by focusing on critical fault detection mechanisms while eliminating the redundant overhead of a complete second core, thereby significantly reducing area and power consumption.
Solution Approach 2:
The patent creates a simplified copy of the essential self-testing functionality needed to achieve high fault grading capability, implemented through dedicated support circuitry within the processor core and a self-test controller. This copied functionality provides the necessary fault detection and grading capabilities without requiring a full dual-core implementation, thus reducing area and power consumption while maintaining reliability.
Data Source
AI summary
Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry.