Processor Core Sizing Through Time Modeling for AI Efficiency
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Solution Overview
Problem
Conventional processors struggle to optimize computational efficiency in AI deep learning tasks due to inefficient utilization of computing cores and resource limitations, leading to suboptimal performance in parallel computations.
Innovation Solution
A data processing method that involves obtaining a configuration space for target parameters, building a computational time model, traversing these parameters to find the minimum computational time, and configuring the computational size of each computing core based on the identified parameter to maximize resource utilization and minimize total computational time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the computational size of each computing core is increased to improve parallel computing performance, then the computing efficiency is improved, but the resource utilization and computational time are suboptimal
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the computational size of each computing core based on a computational time model. The system traverses different parameter configurations (first parameter to n-th parameter) and selects the optimal configuration that minimizes computational time while maximizing productivity, thereby resolving the contradiction between computing efficiency and computational time.
Solution Approach 2:
The patent implements dynamics by making the computational size configuration adaptive rather than fixed. The system uses a computational time model to dynamically determine the optimal computational size for each computing core based on real-time performance characteristics, allowing the system to adapt to different computing workloads and achieve optimal balance between productivity and time efficiency.
2Productivity
If conventional processors are used without optimization to simplify device complexity, then the ease of operation is maintained, but the computing efficiency in AI deep learning tasks is suboptimal
Solution Approach 1:
The patent applies self-service by enabling the processor to automatically optimize its own configuration. The system includes a computational time model that self-evaluates different computational size configurations and autonomously determines the optimal settings for each computing core, eliminating the need for external manual optimization while achieving high computing efficiency in AI deep learning tasks.
Solution Approach 2:
The patent implements preliminary action by pre-establishing a computational time model that predicts performance characteristics before actual computing tasks are executed. This model allows the system to pre-determine optimal computational size configurations, preparing the processor in advance for efficient operation without requiring complex real-time adjustments during task execution.
3Measurement precision
If the computational size of computing cores is optimized based on real hardware testing to ensure accuracy, then the measurement precision is improved, but the time consumption and resource usage increase
Solution Approach 1:
The patent applies copying by creating a virtual computational time model that replicates the behavior of actual hardware without requiring physical testing. This virtual model allows the system to evaluate different computational size configurations through simulation rather than real hardware experimentation, achieving high measurement precision while significantly reducing time consumption and resource usage.
Solution Approach 2:
The patent implements preliminary action by pre-building a computational time model that captures hardware behavior characteristics before actual optimization tasks are performed. This preliminary model allows the system to conduct virtual experiments and determine optimal configurations in advance, eliminating the need for time-consuming real hardware testing while maintaining high accuracy in optimization results.
Data Source
AI summary
Techniques for improving computing efficiency of a processor by optimizing a computational size of each computing core in the processor are provided. The techniques include obtaining a configuration space for a target parameter; obtaining a computational time model of the processor, the computational time model is a function of the target parameter and a number of computing cores of the processor; traversing the target parameter in the configuration space, and calculating, based on the computational time model, a computational time corresponding to the target parameter that is selected; in response to the target parameter being a k-th parameter with a minimum computational time, determining the target parameter as the k-th parameter; and improving the computing efficiency of the processor by configuring the computational size of each computing core in the processor based on the k-th parameter.