Processor Core Stressmark Generation for Hard Error Detection
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Solution Overview
Problem
Multi-processor computer systems are vulnerable to hard faults exacerbated by aging and harsh environmental conditions, leading to discarded processor cores and inefficiencies, as current verification tests are workload-agnostic and focus on transient errors rather than hard errors, failing to detect issues before system performance is compromised.
Innovation Solution
A method for customizing the generation and application of stress test conditions in processor cores by analyzing workload-specific switching activity levels, generating stressmarks to target specific macros, and using machine learning to predict thresholds, allowing for proactive error detection and prevention of power viruses, thereby reducing processor core discard and improving system efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If workload-agnostic verification tests are used, then implementation is simple, but detection precision for hard errors is insufficient
Solution Approach 1:
The system performs preliminary analysis of workload characteristics before generating stressmarks. By pre-characterizing the workload to identify active macros and their switching patterns, the system prepares targeted test conditions in advance, enabling precise hard error detection without requiring complex runtime verification infrastructure.
Solution Approach 2:
The verification approach is segmented into distinct phases: workload characterization, stressmark generation, and targeted verification. By dividing the verification process into these segments, each handling specific aspects of error detection, the system achieves high precision for hard errors while managing complexity through modular organization.
2Reliability
If comprehensive stress testing is applied to all processor cores, then reliability improves, but productivity decreases due to resource loss
Solution Approach 1:
The system applies verification resources locally and selectively to only those processor cores and macros that are currently active and vulnerable based on workload analysis. By concentrating verification efforts on relevant targets rather than uniformly testing all cores, the system maintains high reliability for active components while minimizing productivity impact from unnecessary testing.
Solution Approach 2:
The system performs partial verification by generating stressmarks that target only the specific macros and functional units active during the current workload, rather than applying comprehensive stress testing to the entire processor. This partial action approach provides sufficient reliability for the active workload while preserving system efficiency.
3Reliability
If frequency guard bands are increased to prevent errors, then reliability improves, but use of energy increases
Solution Approach 1:
The system uses feedback from workload characterization and runtime monitoring to dynamically adjust verification intensity. By continuously monitoring macro activity and switching patterns, the system adapts stressmark generation to actual processor state, providing reliable error detection only when and where needed, thereby avoiding unnecessary energy consumption from constant high-frequency guard band operations.
Data Source
AI summary
A computer-implemented method, a computer system and a computer program product customize generation and application of stress test conditions in a processor core. The method includes receiving a workload at the processor core, where the workload includes a plurality of instructions and the processor core comprises a plurality of macros. The method also includes obtaining macro performance data for each macro in the plurality of macros from the processor core. The method further includes determining a switching activity level for each macro in the plurality of macros when each instruction in the plurality of instructions is run based on the macro performance data. Lastly, the method includes generating a stressmark comprising the plurality of instructions in the workload, where the stressmark is associated with a macro in the plurality of macros when the switching activity level for the macro is above a minimum threshold.