Processor Core Testing via Segmented Parallel Operation
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Solution Overview
Problem
Current methods for testing computer cores in computing units with multiple cores are limited in error detection and can only temporarily block processing units, restricting test patterns and coverage, which is inadequate for real-time systems and safety-critical applications.
Innovation Solution
A method where one computer core is tested during normal operation while the other processes the program flow, using existing test patterns and scan chains to achieve high error coverage without interrupting the system, allowing for real-time testing and continuous functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a computer core is tested using conventional methods, then error detection is performed, but the processing unit is blocked for a short time and test coverage is limited
Solution Approach 1:
The computing unit is divided into multiple computer cores, allowing one core to be tested while others continue processing. This segmentation enables parallel operation where test execution on one core does not block the entire system, resolving the contradiction between error detection and processing continuity.
Solution Approach 2:
An internal connection system acts as an intermediary between computer cores, enabling test data and control signals to be transmitted without blocking the processed data flow. This mediator allows test operations to proceed simultaneously with normal processing operations on different cores.
2Reliability
If test patterns are extended to improve error coverage, then better fault detection is achieved, but the test duration increases and system availability decreases
Solution Approach 1:
By segmenting the processing system into multiple independent cores, the patent enables extended test patterns to be applied to one core without affecting overall system availability. Other cores continue processing, maintaining productivity while allowing comprehensive testing on the targeted core.
Solution Approach 2:
The system implements periodic testing where tests are executed at intervals rather than continuously blocking the system. This allows extended test patterns to be applied periodically to improve coverage while maintaining system availability between test cycles through parallel processing on other cores.
3Reliability
If a computer core is switched to test mode, then detailed testing can be performed, but the core is no longer available for normal processing
Solution Approach 1:
The patent divides the computing unit into multiple independent computer cores, allowing one core to be switched to test mode while others remain in processing mode. This segmentation resolves the contradiction by enabling detailed testing on the test core without impacting the processing capability of the system as a whole.
Solution Approach 2:
Each computer core is designed to be multi-functional, capable of operating in both normal processing mode and test mode. This universality allows cores to dynamically switch between functions based on system needs, enabling detailed testing when required while maintaining full processing capability through other cores.
4Reliability
If test data is loaded using a control unit interface, then testing can be initiated, but the interface and processing unit are occupied during the test
Solution Approach 1:
The internal connection system serves as an intermediary communication channel between computer cores, allowing test data to be transferred without occupying the external control unit interface during the actual test execution. This mediator enables test data loading while keeping the external interface available for other operations.
Solution Approach 2:
Test data is prepared and loaded into intermediate storage structures before the actual test execution begins. This preliminary action allows the control unit interface to be released after initial data loading, while the test proceeds using internal communication paths, reducing interface occupancy during the main test phase.
Data Source
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AI summary
The invention relates to a method and a device for testing a computer core in a processor comprising at least two computer cores, wherein the computer cores (2, 3) are connected to each other via an internal connecting system (7). Both computer cores (2, 3) contribute to the operating flow of a machine. In the method for testing a computer core, with which a high error detection rate can be achieved with minimum time expenditure, a test is run in one computer core, while at the same time in the other computer core a program for carrying out the driving operation of the motor vehicle is processed.