Processor Core Work Placement via Power Control Unit
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Solution Overview
Problem
Conventional speed binning methods treat multicore processors as single-core devices, leading to inefficient work placement on processor cores due to manufacturing variations, resulting in higher power consumption and lower performance.
Innovation Solution
The implementation of a control process that determines work placement on favored cores at the operating system level (driver level) and at a hardware level, using a Power Control Unit (PCU) to identify favored cores based on physical characteristics and dynamically adjust workload distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional speed binning treats multicore processors as single-core devices, then manufacturing variation management is simplified, but work placement efficiency deteriorates and power consumption increases
Solution Approach 1:
The patent segments the multicore processor into individually characterized cores, each with its own speed and power bin attributes. Instead of treating the processor as a single entity, the system divides it into discrete core units that can be independently evaluated and assigned workloads based on their specific performance characteristics.
Solution Approach 2:
The patent applies local quality by assigning different speed bins and power bins to different cores based on their individual performance characteristics. Each core receives a tailored classification reflecting its actual capabilities, allowing optimal work placement that matches specific core strengths rather than applying a uniform classification to all cores.
2Reliability
If conventional speed binning uses the slowest core's speed for the entire processor, then reliability is improved, but overall processor performance deteriorates
Solution Approach 1:
The patent introduces dynamic work placement that adapts to individual core capabilities. The system dynamically assigns workloads to appropriate cores based on their speed bin classifications, allowing the processor to operate at optimal performance levels for each task rather than being constrained by the slowest core's speed.
Solution Approach 2:
The patent changes the parameter used for processor classification from a single conservative speed value to multiple individual core speed bins. This parameter transformation allows each core to be classified according to its actual performance characteristics, enabling more accurate work placement and better overall processor utilization.
3Reliability
If conservative guard bands are employed during testing, then quality and reliability are maintained, but power efficiency deteriorates
Solution Approach 1:
The patent introduces power binning as an additional classification parameter alongside speed binning. This dual-parameter approach allows the system to identify and assign power-efficient cores for appropriate workloads, optimizing power consumption while maintaining the quality and reliability ensured by conservative testing guard bands.
Data Source
AI summary
Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.