Processor Communication Synchronization With Local Count Reflectors
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Solution Overview
Problem
Existing methods for synchronizing inbound and outbound message processing between multiple processors introduce data latency, require external hardware, and increase system complexity and power consumption, especially when processors operate asynchronously due to clocking or architectural differences.
Innovation Solution
A system utilizing a reflector, such as a SINC, to synchronize processors by reflecting local counts to remote counts in real time through PCIe addressing, ensuring synchronized execution of applications and processes across multiple processors with minimal hardware and memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If network switch loopback is used to synchronize inbound and outbound message processing, then synchronization is achieved, but data latency increases and external hardware requirements increase
Solution Approach 1:
The patent extracts the synchronization function from external hardware (network switch) and implements it within the processor itself using local memory and counters. This eliminates the need for external hardware involvement in the synchronization process, thereby reducing data latency while maintaining synchronization reliability.
Solution Approach 2:
The patent introduces an intermediary mechanism (local counters and memory locations within the processor) that mediates between inbound and outbound message processing. This intermediary tracks message counts and enables synchronization without requiring external hardware, thus reducing latency.
2Reliability
If additional shared memory is used to synchronize processors, then synchronization is achieved, but hardware requirements increase and power consumption increases
Solution Approach 1:
The patent implements synchronization using local memory locations and counters within each processor rather than requiring additional shared memory hardware. This local implementation reduces hardware requirements and the associated power consumption while achieving the same synchronization effect.
3Reliability
If additional shared memory is used to synchronize processors, then synchronization is achieved, but system complexity increases
Solution Approach 1:
The patent extracts the synchronization functionality from complex external hardware (shared memory systems) and implements it using simple local counters and memory locations within each processor. This simplifies the overall system architecture while maintaining synchronization capability.
4Reliability
If additional shared memory is sized to accommodate worst-case skew, then synchronization is achieved, but memory size becomes larger than desired
Solution Approach 1:
The patent uses partial action by implementing synchronization with minimal local memory resources (counters and small memory locations) rather than allocating excessive memory to accommodate worst-case scenarios. The counters track message processing states efficiently without requiring large memory allocations.
Data Source
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AI summary
A system, method and computer program product synchronize a plurality of processes of one or more applications executed by a plurality of processors. In addition to the processors, the system includes a plurality of memories with each memory associated with a respective process and configured to maintain a local count representative of a message of the respective process with which the memory is associated and at least one remote count representative of a message of a corresponding process executed by another processor. The system also includes a reflector configured to reflect the local count of the respective process to a remote count of the corresponding process. For synchronization, a first process of a first application executed by a first processor is configured to enter a delay period if the local count and at least one remote count maintained by the memory associated with the first process fail to match.