Processor ISA Extension for Cryptographic Operations
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Solution Overview
Problem
Existing methods for implementing block cipher algorithms in processors either require significant additional hardware resources or rely on outdated instructions, limiting flexibility and performance.
Innovation Solution
A processor operation method that executes different operations based on address information, using a dedicated buffer to store operands and address information, allowing for new cryptographic operations without modifying the instruction set architecture (ISA) or compiler, and applying hardware masking for power analysis resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a programmable cryptographic coprocessor is used to execute block ciphers, then execution speed is improved, but hardware resources and cost are significantly increased
Solution Approach 1:
The patent makes the existing CPU core universal by enabling it to execute both general-purpose instructions and cryptographic operations through ISA extension. The CPU core can dynamically switch between standard instructions and cryptographic instructions (such as SubBytes and MixColumns for AES) without requiring a separate dedicated coprocessor, thus achieving multi-functionality with existing hardware resources.
Solution Approach 2:
The patent merges cryptographic processing capabilities directly into the existing CPU core by extending the instruction set architecture. Instead of keeping cryptographic operations separate in a dedicated coprocessor, the cryptographic instructions are integrated into the CPU's instruction pipeline, allowing unified processing of both general computation and cryptographic operations within a single core.
2Adaptability or versatility
If the CPU core is extended to support cryptographic operations through ISA extension, then flexibility is improved, but the supported algorithms are outdated and performance is limited
Solution Approach 1:
The patent implements dynamic cryptographic processing where the CPU core can adaptively execute different cryptographic algorithms based on runtime conditions. The ISA extension allows the processor to dynamically switch between standard instructions and cryptographic instructions, enabling support for both traditional algorithms (AES, DES) and newer algorithms without requiring static hardware configuration for each algorithm.
Solution Approach 2:
The patent changes the operational parameters of the CPU core by introducing new cryptographic instructions that modify the instruction set architecture. These parameter changes include adding specialized opcodes for cryptographic operations, extending register usage for cryptographic purposes, and adjusting the control flow to handle cryptographic-specific requirements, thereby enabling support for modern algorithms while maintaining backward compatibility.
3Device complexity
If cryptographic operations are executed using standard CPU instructions, then hardware resources are saved, but execution speed is reduced compared to dedicated hardware
Solution Approach 1:
The patent extracts critical cryptographic operations from the general-purpose instruction flow and implements them as dedicated cryptographic instructions within the CPU core. By taking out operations like SubBytes, MixColumns, and other algorithm-specific steps and giving them dedicated instruction support, the processor achieves faster execution of these operations without requiring a completely separate hardware coprocessor.
Solution Approach 2:
The patent prepares the CPU core in advance for cryptographic operations by pre-configuring the extended ISA with cryptographic instructions and pre-allocating necessary register resources. The processor pipeline is pre-adapted to handle cryptographic instruction sequences efficiently, reducing the overhead that would otherwise slow down cryptographic execution when using standard general-purpose instructions.
4Productivity
If additional control logic gates, register files, and memory are added to support cryptographic operations, then cryptographic performance is improved, but device complexity and cost are increased
Solution Approach 1:
The patent makes existing CPU components universal by designing them to handle both general-purpose and cryptographic workloads. The register files, control logic, and memory interfaces are extended to support cryptographic operations alongside standard computing tasks, eliminating the need for separate dedicated hardware resources for cryptography.
Solution Approach 2:
The patent merges cryptographic processing functions into the existing CPU architecture by integrating cryptographic instructions into the instruction pipeline and utilizing existing hardware resources for dual purposes. This combination approach allows the processor to achieve cryptographic capability without adding separate control logic gates, register files, or memory structures.
Data Source
AI summary
Disclosed are a processor, a processor operation method and an electronic device comprising same. The disclosed processor operation method comprises the steps of: identifying an instruction for instructing the execution of a first operation and address information of an operand corresponding to the instruction; and executing the instruction on the basis of whether or not the address information of the operand satisfies a predetermined condition. In the step of executing the instruction, a second operation configured to the instruction is executed for the operand if the address information of the operand satisfies the predetermined condition, and the first operation is executed for the operand if the address information of the operand does not satisfy the predetermined condition.