Processor Data Access Device with Duplication Circuit
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Solution Overview
Problem
In conventional processor circuits, the instruction fetch and data load/store stages contend for access to the instruction cache memory, leading to reduced operation efficiency due to simultaneous requests for instruction and data retrieval.
Innovation Solution
A data access device and method that includes an instruction cache memory, a data cache memory, a processor circuit, a duplication circuit, and a decision circuit, where specific data is copied from the instruction cache to the data cache memory after the Nth read, allowing the processor to read from the data cache for the Mth time, reducing contention for the instruction cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the processor circuit reads data from the instruction cache memory in the data load/store stage, then the data can be accessed from the same cache memory, but the instruction fetch stage and data load/store stage contend for access opportunity, reducing operation efficiency
Solution Approach 1:
The patent divides the cache memory into two separate entities: an instruction cache memory (ICache) for storing instructions and a data cache memory (DCache) for storing data. This segmentation allows the instruction fetch stage and data load/store stage to access different cache memories simultaneously, eliminating contention and improving operation efficiency while maintaining a relatively simple overall cache structure
Solution Approach 2:
The patent introduces a duplication circuit as an intermediary component that copies data from the instruction cache memory to the data cache memory when data is first loaded. This intermediary mechanism enables subsequent data accesses to be served from the data cache memory without contending with the instruction fetch stage for access to the instruction cache memory
2Reliability
If the processor waits for one stage to finish accessing the instruction cache memory before the other stage accesses it, then the cache memory access is serialized, but this waiting mechanism reduces operation efficiency
Solution Approach 1:
By segmenting the cache memory into instruction cache and data cache, the patent enables parallel access paths for instruction fetch and data load/store operations. Each stage has its own dedicated cache memory, eliminating the need for serialization and waiting, thus reducing access waiting time while maintaining access correctness through dedicated access paths
Solution Approach 2:
The duplication circuit performs preliminary action by copying data from the instruction cache memory to the data cache memory when data is first loaded into the instruction cache. This preliminary duplication ensures that subsequent data accesses can be served from the data cache memory without waiting for instruction cache access, eliminating waiting time while ensuring data correctness
Data Source
AI summary
The present invention discloses a data access device and method applicable to a processor. An embodiment of the data access device comprises: an instruction cache memory; a data cache memory; a processor circuit configured to read specific data from the instruction cache memory for the Nth time and read the specific data from the data cache memory for the Mth time, in which both N and M are positive integers and M is greater than N; a duplication circuit configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Nth time; and a decision circuit configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request.