Processor Data Flow Control via Sampling and Identification Signals
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Solution Overview
Problem
Conventional communication systems between processors often experience data loss due to overflow conditions, requiring additional instructions for synchronization, which increases time and design complexity, reducing efficiency.
Innovation Solution
A processor system with a sampling controller, sampling circuit, and data flow controller that generates control signals based on identifiers and enable signals to manage data flow, eliminating the need for acknowledgement signals and allowing independent operation of processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If acknowledgement signals are used to synchronize data transfer between processors, then data loss is avoided, but execution time and design complexity significantly increase
Solution Approach 1:
The patent applies preliminary action by pre-configuring data transfer parameters (data count, identifiers, enable signals) before actual data transfer begins. The sampling controller is pre-programmed with the number of data packets to transfer, allowing it to automatically control the transfer process without requiring real-time acknowledgements, thus eliminating waiting time while maintaining data integrity.
Solution Approach 2:
The system implements self-service through the sampling controller's ability to autonomously manage data transfer based on pre-loaded parameters. The controller independently samples data counts, generates control signals, and manages the transfer process without external intervention or acknowledgement signals, reducing both time and complexity while ensuring reliable transfer.
2Reliability
If acknowledgement signals are used to synchronize data transfer between processors, then data loss is avoided, but design complexity significantly increases
Solution Approach 1:
The patent extracts the synchronization function from the data transfer path by separating control signal generation from the main data flow. The sampling controller independently generates control signals based on pre-configured parameters, removing the need for complex acknowledgement handshaking mechanisms while maintaining reliable data transfer.
Solution Approach 2:
The sampling controller performs self-service by autonomously managing the entire data transfer process using pre-loaded parameters. It independently samples data counts, generates control signals, and monitors transfer completion without requiring external control logic or acknowledgement handling, significantly simplifying the overall system design.
3Productivity
If processors operate independently without synchronization, then processing speed increases, but data loss occurs due to overflow conditions
Solution Approach 1:
The patent applies preliminary action by pre-configuring the sampling controller with exact data transfer parameters (data count, identifiers, enable signals) before transfer begins. This allows the receiver processor to be perfectly prepared to accept incoming data packets without overflow, enabling independent high-speed operation while guaranteeing data integrity through advance parameter setup.
Data Source
AI summary
First and second processors that are in communication with each other are disclosed. The first processor includes a sampling controller, a sampling circuit, and a data flow controller. The sampling controller is configured to receive multiple identifiers and corresponding enable signals associated with data that is to be transmitted to or received from the second processor, and generate an identification signal and a sampling signal based on one of the identifiers and the corresponding enable signal. The sampling circuit is configured to sample multiple data counts to generate corresponding sampled counts based on the identification signal and the sampling signal. The data flow controller is configured to generate a control signal based on the identifiers, the corresponding enable signals, the data counts, and the corresponding sampled counts to control data flow between the first and second processors.