Multi-core Processor Internal Data Transfer Circuit Polling Mechanism
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Solution Overview
Problem
Existing multi-core processors face inefficiencies in data transfer between processor cores due to high access latency of external memory, which affects overall packet forwarding processing efficiency.
Innovation Solution
A multi-core processor design that incorporates an internal data transfer circuit and a polling mechanism to facilitate fast data transfer between processor cores, eliminating the need for external memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If external memory and external bus are used for data transfer between processor cores, then power consumption and cost requirements are met, but data transfer efficiency deteriorates due to high access latency
Solution Approach 1:
An internal data transfer circuit is introduced as an intermediary component between processor cores, replacing the need for external memory and bus communication. This mediator enables direct data exchange between cores, reducing access latency while maintaining acceptable power consumption levels.
Solution Approach 2:
The data transfer architecture transitions from a hierarchical external memory access model to a peer-to-peer internal transfer model. By changing the dimensional relationship between processor cores and data storage, the system achieves faster access times without significantly increasing power consumption.
2Device complexity
If external memory is used for data transfer between processor cores, then device complexity is reduced, but productivity deteriorates due to slow data access
Solution Approach 1:
The data transfer circuit is merged with the processor core structure, creating an integrated solution that combines data processing and data transfer functions within the same device. This integration improves productivity by enabling faster data access while maintaining manageable device complexity through unified architecture.
3Speed
If polling mechanism is implemented for data transfer, then data transfer speed improves, but device complexity increases due to additional control logic
Solution Approach 1:
The polling mechanism enables processor cores to autonomously check for data availability and initiate transfers without requiring complex external control logic. Each core independently polls the data transfer circuit, allowing the system to achieve high data transfer speeds while keeping the control logic distributed and relatively simple.
Data Source
AI summary
A multi-core processor includes a plurality of processor cores and a data transfer circuit. The processor cores include a first processor core and a second processor core. The first processor core has a first buffer, and writes a first data into the first buffer. The second processor core has a second buffer. The data transfer circuit performs a polling operation upon the first buffer to check if the first buffer has data waiting to be transferred, and transfers the first data from the first buffer to the second buffer, wherein the first data is transferred inside the multi-core processor only.