Processor Debugging Interface Bus Load Reduction
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Solution Overview
Problem
Classic processor architectures face performance penalties due to the critical nature of the access bus for memory and peripheral units, and existing debugging interfaces are not optimally designed for read/write accessibility of internal registers without overloading the access bus or increasing the number of components.
Innovation Solution
A debugging interface with a selecting circuit and access means that allows the processing unit to read/write internal resources directly, using a communication register with an address field and control field to manage access modes, reducing the load on the access bus and minimizing additional components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If internal registers of the debugging interface are made directly accessible to the processing unit through the access bus, then the processing unit can read/write internal resources, but the access bus becomes overloaded and system performance deteriorates
Solution Approach 1:
A communication register is introduced as an intermediary between the processing unit and the internal debugging interface registers. The communication register acts as a buffer that receives data from the processing unit and forwards it to the internal registers through the existing access bus, thereby enabling accessibility without directly loading the bus with frequent access requests.
Solution Approach 2:
The access path is segmented into two stages: first, the processing unit accesses the communication register; second, the communication register transfers data to the internal registers. This segmentation allows the processing unit to operate independently from the internal register access mechanism, reducing direct bus contention.
2Adaptability or versatility
If internal registers are made accessible to the processing unit, then debugging capability is improved, but the number of additional components increases
Solution Approach 1:
The communication register serves multiple functions: it acts as a buffer for data transfer, a control interface for the processing unit, and a mediator for accessing internal registers. By making this single component multi-functional, the patent avoids adding multiple separate components to achieve the same functionality.
Solution Approach 2:
The communication register merges the functions of data buffering, control signaling, and register mapping into a single integrated component. This consolidation reduces the overall component count while maintaining full debugging capability and processing unit accessibility.
Data Source
AI summary
The systems and methods disclosed relate to a processor comprising a processing unit and a debugging that which can be connected to an external emulator for debugging a program executed by the processor, the debugging interface including internal resources at least partially accessible to the external emulator. According to one embodiment, the debugging interface includes a selecting circuit for selecting an internal resource of the debugging interface, according to a reference supplied by the processing unit, and an access circuit that transfers a datum between the resource selected and a data field accessible by the processing unit.