Processor Debug Unit Interrupt-Free Data Exchange
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Solution Overview
Problem
Existing communication channels between processors and debuggers for debugging are inefficient, often requiring interrupts that occupy resources and result in slow responses due to low interrupt priority.
Innovation Solution
A debug unit within the processor, including write and read registers with flag bits to indicate data validity, and a control unit that manages access based on these flags, allowing for efficient data transmission without interrupts and optimizing communication by generating jump requests to facilitate rapid data exchange.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interrupt-based communication channel is used between processor and debugger, then data transmission can be established, but response speed is slow and resources are occupied due to low interrupt priority
Solution Approach 1:
The patent extracts the communication function from the interrupt-based system and creates a dedicated debug unit with independent read/write registers and flag bits within the processor. This separation allows debug communication to occur independently from the main interrupt handling system, eliminating the need for low-priority interrupts and enabling faster response times without occupying interrupt resources.
2Productivity
If interrupt-based communication is used, then processor-debugger communication is established, but interrupt resources are occupied
Solution Approach 1:
The patent introduces a dedicated debug unit as an intermediary component between the processor and debugger. This unit includes specialized registers (read/write registers) and control mechanisms (flag bits) that mediate all communication, eliminating the need for the processor to directly handle debug interrupts. The intermediary handles all debug communication tasks, freeing up processor resources while maintaining efficient debugging capability.
3Reliability
If flag bits are used to indicate data validity, then access control is improved, but device structure becomes more complex
Solution Approach 1:
The patent merges the data storage function and the status indication function into unified register structures. Each register (read register and write register) contains both the actual data and associated flag bits (kernel read flag bit, kernel write flag bit) within the same register entity. This integration reduces the need for separate status registers and simplifies the overall structure while ensuring reliable data access control through the combined data-flag register design.
Data Source
AI summary
The present disclosure discloses a debug unit, comprising: a write register configured to store kernel write data written by a kernel of a processor, wherein the processor is communicatively coupled to a debugger configured to read the kernel write data, wherein the kernel write data is associated with a kernel write flag bit to indicate data validity of the kernel write data; and a control unit including circuitry configured to control access to the write register by the kernel of the processor and the debugger based on data validity indicated by the kernel write flag bit. The present disclosure further discloses a corresponding processor including the debug unit, a corresponding debugger communicatively coupled to the processor, and a corresponding debug system including the processor coupled to the debugger.