Processor Division Loop Correction for Quotient Accuracy

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Solution Overview

Problem

Existing division operation methods using loop operations face complexity and increased power consumption due to the need for additional processes like quotient fix operations and remainder fix operations, especially when the initial loop count value is not a multiple of the bit width, leading to incorrect final quotients and increased circuit size and latency.

Innovation Solution

A processor design that includes a dividend zero count value counter, a divisor zero count value counter, a correction value calculator, and shift units to adjust the dividend and divisor, allowing for a correction loop count value that ensures the loop count becomes a multiple of the bit width, thereby eliminating the need for additional fix operations and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the initial loop count value is not a multiple of the bit width, then additional fix operations are required, but this increases circuit complexity and power consumption

Engineering Contradiction:
Improvecorrectness of final quotientVSAvoidcircuit size
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent adjusts the dividend and divisor values before the division operation begins, specifically modifying the dividend by adding a correction value when the loop count is not a multiple of the bit width. This preliminary adjustment ensures that the division can be completed in exactly the intended number of cycles without requiring additional fix operations afterward, thereby eliminating the need for extra correction circuits while maintaining computational correctness

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If additional fix operations are performed to correct the final quotient, then the quotient accuracy is improved, but the processing time and latency increase

Engineering Contradiction:
Improvequotient accuracyVSAvoidprocessing latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The correction value is calculated and applied to the dividend before the division operation starts. By adjusting the dividend in advance based on the loop count modulo the bit width, the patent ensures that the division completes exactly in the predetermined number of cycles, eliminating the need for time-consuming post-operation fix corrections and reducing overall processing latency

Inventive Principle:
Principle #10Preliminary action

3Reliability

If additional fix operations are implemented to handle non-multiple loop counts, then the division correctness is improved, but the power consumption increases

Engineering Contradiction:
Improvedivision correctnessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent calculates the correction value based on the loop count and bit width relationship before division begins, then applies this correction to the dividend. This preliminary adjustment eliminates the need for power-consuming fix operations during or after the division process, as the corrected dividend ensures the loop count will be properly aligned with the bit width from the start

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts and handles the correction requirement separately from the main division operation by calculating the correction value based on the modulo operation result. This separation allows the correction to be applied once at the beginning rather than requiring repeated fix operations, thereby reducing overall power consumption while ensuring division correctness

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9009209B2Processor, control method of processor, and computer readable storage medium storing processing program for division operation
Publication Date: 2015.04.14 FUJITSU LTD
  • US9009209B2 patent drawing
  • US9009209B2 patent drawing
  • US9009209B2 patent drawing

AI summary

A processor for dividing by calculating repeatedly an n-bit width partial quotient includes, a dividend zero count value counter that counts a dividend zero count value, a divisor zero count value counter that counts a divisor zero count value, a correction value calculator that calculates a correction value to a loop count value, a correction loop count value calculator that calculates a correction loop count value, a dividend shift unit that shifts leftward an absolute value of the dividend by the dividend zero count value and shifts rightward the leftward-shifted absolute value of the dividend by the correction value, a divisor shift unit that shifts leftward an absolute value of the divisor by the divisor zero count value, and a division loop operation unit that divides based on an output value from the dividend shift unit, an output value from the divisor shift unit, and the correction loop count value.