Processor Domain Clock Frequency Gating for Power Management
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Solution Overview
Problem
The increasing power requirements and energy consumption of computing systems, particularly in multicore processors, pose a significant challenge for energy efficiency and conservation, as they contribute substantially to overall electricity usage and demand more efficient power management solutions.
Innovation Solution
The implementation of integrated voltage regulators (IVRs) and power control units (PCUs) within multicore processors allows for fine-grained control of voltage and power management, enabling independent operation of each core and domain, along with dynamic voltage frequency scaling (DVFS) and dynamic workload swapping between cores, to optimize power consumption based on workload and thermal constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple hardware threads, multiple cores, and increased integrated circuit density are implemented to enhance computing capability, then processing power and functionality are improved, but power requirements and energy consumption escalate significantly
Solution Approach 1:
The processor is divided into multiple independent power domains, each capable of being controlled separately. This allows selective activation of only those domains needed for current workloads, reducing overall power consumption while maintaining high processing capability when required.
Solution Approach 2:
The patent implements dynamic voltage and frequency scaling (DVFS) at the domain level, allowing each domain to adjust its operating parameters in real-time based on workload demands. This dynamic adaptation enables the system to optimize the trade-off between processing power and energy consumption continuously.
2Use of energy by moving object
If dynamic voltage frequency scaling and independent core operation are implemented to optimize power consumption, then energy efficiency is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
Multiple power control units (PCUs) are integrated into a single unified structure that manages all power domains collectively. This merging approach provides fine-grained control capability while reducing the overall complexity compared to having completely independent control mechanisms for each core or domain.
Solution Approach 2:
The power control unit is designed as a universal controller that can manage multiple power domains with different voltage and frequency requirements. This multi-functional design consolidates control logic and reduces system complexity while maintaining the ability to optimize power consumption across diverse operational scenarios.
Data Source
AI summary
In an embodiment, a processor includes at least one core, a first domain to operate at a first clock frequency, and a second domain to operate at a second clock frequency that is lower than the first clock frequency. The processor also includes phase locked loop (PLL) logic to generate a first signal having a first frequency corresponding to the first clock frequency and to provide the first signal to the first domain. The processor also includes a first clock to produce a first squash signal that is determined based at least in part on the second clock frequency, and also first logic to generate a second signal having a second frequency corresponding to the second clock frequency by gating the first signal with the first squash signal and to provide the second signal to the second domain. Other embodiments are described and claimed.