Processor DRAM Bypass for In-Field Test Scan Data Storage
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Solution Overview
Problem
Conventional in-field testing of processor-based systems lacks comprehensive testing coverage due to limitations in accessing and storing large-sized test scan data, which is crucial for identifying and repairing defects effectively.
Innovation Solution
The integration of external dynamic random access memory (DRAM) within the processor-based system allows for storing and accessing larger-sized test scan data, enabling the built-in testing system to perform more extensive functional tests by bypassing the memory controller during the testing mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional in-field testing methods are used, then the testing process is simple and can be performed with existing resources, but the testing coverage is insufficient due to inability to store and access large-sized test scan data
Solution Approach 1:
The patent merges the test scan data storage function with the existing system DRAM, combining two separate memory requirements into a single memory resource. The DRAM is used for both system operation and test data storage, eliminating the need for separate test memory infrastructure and reducing overall system complexity while enabling comprehensive testing.
Solution Approach 2:
The system DRAM is designed to serve multiple functions: it acts as both the system memory for normal operation and as the test scan data storage medium for in-field testing. This multi-functionality allows the same hardware resource to support both operational and testing requirements, improving testing coverage without adding dedicated test memory components.
2Reliability
If larger-sized test scan data is stored in internal memory, then testing coverage improves, but the memory capacity is insufficient and access time increases
Solution Approach 1:
The patent transitions from limited internal memory storage to external DRAM storage, moving the test data storage capacity to a different dimensional space with significantly larger capacity. This external DRAM approach provides abundant storage space for comprehensive test scan data while maintaining acceptable access times through the memory controller interface.
3Ease of operation
If the memory controller is used during testing mode, then data access is streamlined, but the controller may interfere with testing operations due to potential defects
Solution Approach 1:
The patent extracts the memory controller from the test data access path during testing operations. By bypassing the memory controller and providing direct access pathways to the DRAM for test scan data retrieval, the system eliminates potential interference from defective controllers while maintaining efficient data access. This separation ensures testing accuracy is not compromised by controller defects.
Data Source
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AI summary
Processor-based system supporting in-field testing using external dynamic random access memory (DRAM) for storing and accessing test scan data. The processor-based system includes a processor that includes one or more central processing units (CPUs) that each have access to resources, such as cache memory, a memory controller to access system memory (e.g., DRAM), interfaces circuits, to perform tasks by executing of program code. The processing-based system includes an internal, built-in testing system that allows the processor-based system to be placed into test mode to perform in-field testing of the processor-based system. To support larger-sized scan data, the processor-based system is configured for the built-in-test system to access test scan data stored in DRAM in the processor-based system in a test mode. In this manner, the DRAM supports storing larger-sized test scan data so that greater in-field test coverage can be performed in the processor-based system.