Multi-thread Processor Dynamic CPU Bandwidth Allocation
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Solution Overview
Problem
Multi-threaded processors face challenges in dynamically allocating CPU bandwidth among threads and timely handling of interrupts, particularly when dealing with unequal or changing CPU allocations and interrupt masking across multiple threads.
Innovation Solution
A multi-thread superscalar processor with a re-programmable thread map register that dynamically allocates CPU cycles to each thread, allowing for granular control of thread bandwidth and separate interrupt handling for each thread, enabling concurrent processing of multiple protocols like Bluetooth and WLAN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multi-threaded processor uses fixed CPU bandwidth allocation (e.g., 50% per thread), then thread execution is simplified and protected during stalls, but dynamic allocation requirements cannot be met and unequal bandwidth distribution is not possible
Solution Approach 1:
The patent implements dynamic CPU bandwidth allocation by allowing the thread map register to be reprogrammed at runtime, enabling the allocation percentage for each thread to change from fixed to variable based on operational requirements. This resolves the contradiction by introducing adaptability while managing complexity through structured control mechanisms.
Solution Approach 2:
The patent segments CPU bandwidth into discrete allocatable units through the thread map register, which can be configured to assign different percentages to different threads. This segmentation enables unequal and dynamic allocation while maintaining a manageable control structure, resolving the adaptability-complexity contradiction.
2Reliability
If interrupts are masked during handling to prevent re-entry, then interrupt handling completeness is ensured, but timely recognition of new interrupts during pending handling is not possible
Solution Approach 1:
The patent assigns separate interrupt masks to each thread, segmenting the interrupt handling mechanism. This allows one thread to mask interrupts while others continue to recognize and handle new interrupts, ensuring both completeness for the active thread and timeliness for others, thus resolving the contradiction.
Solution Approach 2:
The patent implements partial masking where only the specific thread handling the interrupt masks its own interrupts, while other threads remain unmasked and can still recognize new interrupts. This partial action approach ensures completeness for the active handler while maintaining responsiveness for other threads.
3Device complexity
If a single processor handles multiple protocols (e.g., Bluetooth and WLAN), then device complexity is reduced, but timely protocol-specific interrupt handling and dynamic resource allocation become difficult
Solution Approach 1:
The patent segments protocol handling into separate threads (e.g., Bluetooth thread and WLAN thread), each with its own program counter, register file, and interrupt mask. This segmentation allows independent and timely handling of protocol-specific interrupts while maintaining a single processor architecture, resolving the contradiction between device complexity and productivity.
Solution Approach 2:
The patent enables dynamic allocation of processor resources to different protocols through the reprogrammable thread map register. This allows the system to adjust CPU bandwidth allocation between Bluetooth and WLAN handling based on real-time needs, improving protocol handling efficiency while keeping the overall architecture simple.
Data Source
AI summary
A communication processor is operative to adapt the thread allocation to communications processes handled by a multi-thread processor on an instruction by instruction basis. A thread map register controls the allocation of each processor cycle to a particular thread, and the thread map register is reprogrammed as the network process loads for a plurality of communications processors such as WLAN, Bluetooth, Zigbee, or LTE have load requirements which increase or decrease. A thread management process may dynamically allocate processor cycles to each respective process during times of activity for each associated communications process.