Processor Instruction Scheduling for Performance and Responsiveness
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Solution Overview
Problem
Existing processor technologies face challenges in simultaneously guaranteeing the performance of one instruction stream while providing high responsiveness for another instruction stream, as prioritizing performance-guarantee streams can lead to delayed user input processing, and vice versa.
Innovation Solution
The processor extracts instructions from multiple instruction streams based on priority information, allowing simultaneous execution of instructions from different streams, ensuring that performance-guarantee streams complete their tasks within predetermined time periods without delaying non-performance-guarantee streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher priorities are assigned to performance-guarantee instruction streams to ensure they complete within predetermined time periods, then performance guarantee is improved, but responsiveness to user-instructed processes deteriorates
Solution Approach 1:
The patent implements dynamic priority adjustment where the priority of instruction streams is not fixed but changes based on system state. The priority management unit dynamically modifies priorities of first instruction streams (performance-guarantee) and second instruction streams (user-instructed) based on execution status, allowing the system to adapt between performance guarantee mode and responsiveness mode as needed
Solution Approach 2:
The patent performs preliminary priority assignment where priorities are set in advance for different instruction stream types. First instruction streams are preliminarily assigned high priorities to ensure performance guarantees, while second instruction streams are assigned lower priorities. This preliminary configuration enables the system to automatically ensure performance guarantees without requiring real-time intervention, while still allowing responsiveness when performance guarantees are not actively needed
2Loss of time
If higher priorities are assigned to user-instructed instruction streams to improve responsiveness, then responsiveness is improved, but performance guarantee for critical instruction streams deteriorates
Solution Approach 1:
The dynamic priority adjustment mechanism allows the system to switch between favoring user-instructed streams (for responsiveness) and performance-guarantee streams (for reliability) based on current execution status. When user interaction is detected, priorities are adjusted to improve responsiveness; when performance guarantees are needed, priorities are adjusted to ensure timely completion of critical streams
3Productivity
If multiple instruction streams are executed in parallel to improve overall processing efficiency, then productivity is improved, but complexity of instruction scheduling increases
Solution Approach 1:
The patent segments instruction streams into two distinct categories: first instruction streams (performance-guarantee) and second instruction streams (user-instructed). This segmentation simplifies the scheduling complexity by applying different priority management strategies to different segments, rather than managing all streams uniformly. The instruction buffer is also segmented into multiple regions corresponding to different instruction streams, enabling independent management of each segment
Solution Approach 2:
The patent changes the parameter of instruction stream priority from a uniform value to differentiated values based on stream type. By introducing priority as a variable parameter that can take different values for different instruction stream categories, the system manages complexity through parameter differentiation rather than through complex scheduling algorithms
Data Source
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AI summary
A processor including L computing units, L being an integer of 2 or greater, the processor comprising: an instruction buffer including M×Z instruction storage areas each storing one instruction, M instruction streams being input in a state of being distinguished from each other, each of the M instruction streams including Z instructions, M and Z each being an integer of 2 or greater, M×Z being equal to or greater than L; an order information holding unit holding order information that indicates an order of the M×Z instruction storage areas; an extraction unit operable to extract instructions from the M×Z instruction storage areas; and a control unit operable to cause the extraction unit to extract L instructions in executable state from the M×Z instruction storage areas in accordance with the order indicated by the order information, and input the instructions into different ones of the L computing units.