Processor Dynamic Voltage Scaling Power Optimization
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Solution Overview
Problem
Embedded processors face challenges in achieving high energy efficiency due to increased power consumption and heat radiation as they become more integrated, with traditional dynamic voltage scaling methods either increasing hardware complexity or reducing performance when reducing power supply voltage.
Innovation Solution
A processor design that incorporates a function unit block and peripheral unit block with dynamic voltage scaling power supplies, allowing for different power supply voltages based on operation modes, and a processing element selector to determine the required unit processors for executing instructions, thereby optimizing power usage without performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the power supply voltage is reduced to decrease power consumption, then power consumption decreases, but the processing performance deteriorates due to increased delay time
Solution Approach 1:
The patent implements dynamic voltage scaling by making the power supply voltage adjustable and changeable based on operational requirements. The system can dynamically switch between different voltage levels (Vdd1 for low power, Vdd2 for high performance) depending on the current task demands, thus resolving the contradiction between power consumption and processing performance.
Solution Approach 2:
The patent changes the physical parameter of power supply voltage to optimize system performance. By having multiple voltage levels available and selectively applying them based on operational mode, the system can achieve low power consumption during idle periods while maintaining high performance when needed, effectively managing the trade-off between energy loss and productivity.
2Loss of energy
If multiple power supply voltages are used to reduce power consumption, then power consumption decreases, but device complexity increases due to the need for level shifter blocks
Solution Approach 1:
The patent segments the processor into functionally independent blocks (ALU, register file, control unit, etc.) that can operate at different voltage levels independently. This segmentation allows the system to apply power optimization selectively to specific blocks without requiring complex level shifters for all inter-block communications, thus reducing overall device complexity while maintaining power savings.
Solution Approach 2:
The patent introduces a voltage control mechanism that acts as an intermediary between the power supply and processor blocks. This mediator intelligently determines which blocks should operate at which voltage levels based on current operational requirements, eliminating the need for complex hardwired level shifter networks while achieving power consumption reduction.
3Productivity
If a parallel-pipeline structure is used to improve processing performance, then processing performance improves, but power consumption increases
Solution Approach 1:
The patent applies dynamic voltage control to the parallel-pipeline structure, allowing the system to operate at high voltage (and thus high performance) only when parallel processing is actually needed. During sequential or low-compute tasks, the voltage is reduced, thereby maintaining processing capability when needed while minimizing power consumption during routine operations.
Solution Approach 2:
The patent implements partial voltage scaling where only specific processor blocks that are actively engaged in parallel processing operations receive high voltage. Other blocks that are idle or performing simple tasks operate at reduced voltage, thus achieving the necessary processing performance for critical paths while avoiding excessive power consumption across the entire processor.
Data Source
AI summary
Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.