Processor Instruction ECC Caching for Shared-Bus Stall Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As process technology advances, memory devices experience increased bit error ratios and decreased yield, necessitating improved error checking and correcting (ECC) circuits to enhance data reliability, but existing systems face inefficiencies due to simultaneous read and write operations on shared data buses, leading to pipeline stalls and performance degradation.
Innovation Solution
A processor and memory system that incorporates an ECC unit to correct errors in instructions and data, storing corrected data in an ECC cache memory and transmitting it to the main cache memory only when a flush condition is met, thereby reducing pipeline stalls and optimizing data bus usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error checking and correcting (ECC) circuits are added to improve data reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines the ECC operation with the existing instruction fetch and data transfer operations. The ECC unit is integrated into the data path between the external memory and the processor, allowing error correction to occur during normal data flow without requiring separate dedicated correction paths or additional control logic.
Solution Approach 2:
The patent introduces an intermediate buffer or storage structure that holds corrected data before it is written back to the cache memory. This intermediary structure allows the ECC unit to operate independently while maintaining the existing memory hierarchy and cache management mechanisms.
2Productivity
If simultaneous read and write operations are performed on shared data buses, then productivity is improved, but reliability deteriorates due to pipeline stalls
Solution Approach 1:
The patent segments the data bus operations by separating read and write transactions into distinct time slots or phases. The ECC correction operations are scheduled to occur during specific windows when the data bus is available, preventing conflicts with simultaneous read/write operations and eliminating pipeline stalls.
Solution Approach 2:
The patent implements dynamic scheduling of ECC operations based on the current state of the data bus and pipeline. The system adaptively determines when to perform ECC correction, when to proceed with read/write operations, and how to manage buffer contents to maintain optimal performance while ensuring data integrity.
Data Source
AI summary
A processor comprising an instruction fetch unit configured to read a first instruction stored in an external memory through a first data bus, generate a first correction instruction in which an error is corrected based on an error checking and correcting (ECC) operation for the first instruction, store an information for the first correction instruction, read a second instruction stored in the external memory through the first data bus according to a second instruction fetch, and transmit the first correction instruction to the external memory through the first data bus based on a flush condition, a decode unit configured to receive and decode the first correction instruction, and an execution unit configured to receive the decoded first correction instruction and execute an operation according to the first correction instruction.