Processor Error Correction Buffering for SRAM Pipeline Stalls
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Solution Overview
Problem
The existing Error Correcting Code (ECC) circuit in processors is inefficient due to its long arithmetic path, which limits operation frequency and causes pipeline stalls when correcting errors in SRAM, leading to reduced instruction execution throughput as it requires multiple cycles for error correction and write-back, preventing continuous instruction delivery.
Innovation Solution
A processing unit with an instruction buffer and program counter buffer that temporarily holds corrected instructions, allowing for selective output and delayed write-back into SRAM, reducing pipeline stalls by enabling continuous instruction delivery even with single-port SRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the ECC circuit is divided into stages to reduce arithmetic path length, then the operation frequency can be improved, but pipeline stalls still occur due to required error correction cycles and write-back operations
Solution Approach 1:
The patent applies preliminary action by performing error correction in advance during the instruction fetch stage, before the instruction is executed. The ECC circuit corrects errors in fetched instructions proactively, and corrected instructions are stored in a buffer. This allows the pipeline to continue executing instructions without waiting for error correction during execution, thereby maintaining high instruction throughput while operating at higher frequencies.
2Reliability
If error correction is performed immediately upon detection, then reliability is improved, but pipeline stalls occur reducing instruction execution throughput
Solution Approach 1:
The patent introduces an intermediary component - a buffer storage - between the ECC circuit and the instruction execution pipeline. When an error is detected and corrected, the corrected instruction is stored in the buffer rather than immediately interrupting the pipeline. The pipeline can then continue fetching and executing subsequent instructions from the buffer, maintaining throughput while ensuring reliability through immediate error correction in the background.
3Device complexity
If a single-port SRAM is used for instruction storage, then hardware size is reduced, but write-back operations cause pipeline stalls
Solution Approach 1:
The patent resolves the single-port SRAM bottleneck by introducing a temporal dimension through buffering. Instead of attempting parallel read-write operations on the same memory port (spatial solution), the system uses a buffer to decouple the timing of read operations (instruction fetch) and write operations (error correction write-back). This allows the single-port SRAM to be used efficiently without causing pipeline stalls, maintaining both hardware simplicity and instruction throughput.
Data Source
AI summary
A processing unit of the embodiments includes an instruction memory that holds a plurality of instructions specified by addresses, and that cannot execute read and write operations concurrently, an error correction circuit that detects and corrects an error in the instruction, a program counter, an instruction buffer that holds the instruction corrected as a corrected instruction, a program counter buffer that holds an address of the instruction where an error has been detected, a selector that selects and outputs any of the output of the error correction circuit and the output of the instruction buffer, and a control unit that controls the read and write of the instruction specified by the address from and into the instruction memory. The control unit writes the corrected instruction in the instruction memory using an address held in the program counter buffer when a predetermined condition is satisfied after the occurrence of the error.