Processor Error Domain Topology for Fault Isolation

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Solution Overview

Problem

Current systems lack the ability for software to accurately and timely diagnose and recover from faults in mission-critical systems due to the inability to discover the association between machine check banks and the execution elements they report errors on, leading to inadequate fault containment and system instability.

Innovation Solution

An instruction set architecture is introduced that allows software to determine the type of machine check bank errors, enabling precise identification of error domains such as socket-scoped, core-scoped, or thread-scoped errors, facilitating targeted diagnostic and recovery actions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If machine check banks are used to log errors, then error detection capability is improved, but the ability to precisely identify fault location and scope deteriorates

Engineering Contradiction:
Improveerror detection capabilityVSAvoidfault location information
Core Design Contradiction:
Measurement precisionVSLoss of information

Solution Approach 1:

The patent segments the machine check bank information into multiple hierarchical levels: socket-level banks, core-level banks, and thread-level banks. Each level contains specific error domain information relevant to that scope. This segmentation allows software to precisely identify fault location by examining the appropriate level, resolving the contradiction between detecting errors and locating them precisely.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary mechanism - the machine check bank topology information structure - that bridges the gap between error detection and fault location. This intermediary contains metadata about which execution elements (threads, cores, sockets) are associated with each machine check bank, enabling software to translate raw error logs into actionable fault location information.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If system shutdown is performed for fault containment, then system reliability is improved, but system availability deteriorates

Engineering Contradiction:
Improvefault containmentVSAvoidsystem availability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent enables local quality control by allowing fault containment at the specific level where the error occurred (thread, core, or socket) rather than forcing a complete system shutdown. Software can isolate and contain errors locally by identifying the specific execution element associated with the machine check bank error, maintaining availability of unaffected system components while ensuring reliability through targeted fault containment.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If machine check banks are shared across multiple execution elements, then resource utilization is improved, but the complexity of discovering error domain associations deteriorates

Engineering Contradiction:
Improveresource sharingVSAvoiderror domain discovery complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent adds another dimension to machine check bank information by including topology metadata that describes the hierarchical relationship between banks and execution elements. Instead of flat error logging, the system now provides multi-dimensional information about which threads, cores, and sockets are associated with each bank. This additional dimension enables software to discover error domain associations systematically without increasing operational complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10223187B2Instruction and logic to expose error domain topology to facilitate failure isolation in a processor
Publication Date: 2019.03.05 INTEL CORP
  • US10223187B2 patent drawing
  • US10223187B2 patent drawing
  • US10223187B2 patent drawing

AI summary

A processor includes an instruction decoder to receive an instruction to perform a machine check operation, the instruction having a first operand and a second operand. The processor further includes a machine check logic coupled to the instruction decoder to determine that the instruction is to determine a type of a machine check bank based on a command value stored in a first storage location indicated by the first operand, to determine a type of a machine check bank identified by a machine check bank identifier (ID) stored in a second storage location indicated by the second operand, and to store the determined type of the machine check bank in the first storage location indicated by the first operand.