Processor Exception Handling Using Branch Target Cache
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Processor exceptions in pipelined processors lead to significant latency and increased power consumption due to multiple stages of flushing and reloading the pipeline, especially during interrupt handling.
Innovation Solution
Implementing an exception cache that stores and provides cached information for specific exception types, allowing the processor to divert program flow directly to the exception address, thereby reducing the need for pipeline flushing and improving response time to exceptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor uses a pipelined instruction fetching unit to fetch instructions during a pipeline period, then instruction fetching efficiency is improved, but latency and power consumption increase during exception handling due to multiple pipeline flushes
Solution Approach 1:
The exception cache pre-stores exception vector addresses and handler information before exceptions occur. When an exception is detected, the cached information is immediately provided to the instruction fetching unit, eliminating the need to flush and refill the pipeline for vector fetch operations. This preliminary caching action resolves the contradiction by maintaining pipeline efficiency while reducing exception handling latency.
Solution Approach 2:
The exception cache acts as an intermediary between the exception detection logic and the instruction fetching unit. Instead of directly flushing the pipeline upon exception detection, the system queries the exception cache for pre-computed vector addresses and handler information, which then guides the instruction fetching unit. This intermediary cache layer eliminates harmful pipeline flushes while maintaining the benefits of pipelined fetching.
2Reliability
If the processor diverts program flow multiple times to handle exceptions (vector fetch, generic handler, specific handler), then exception handling completeness is improved, but power consumption increases due to needlessly fetched instructions
Solution Approach 1:
The exception cache pre-computes and stores the final specific handler addresses along with identification information about the exception type and cause. When an exception occurs, the system can directly jump to the pre-identified specific handler without executing generic handlers that would otherwise cause additional program flow diversions. This preliminary preparation reduces the number of branch instructions executed and eliminates power consumption from fetching instructions in generic handlers when direct routing is possible.
Solution Approach 2:
The exception cache provides feedback information about the exception cause and type to the exception handling logic. This feedback enables the system to determine whether a direct jump to a specific handler is appropriate or whether the traditional multi-stage routing (vector → generic handler → specific handler) is needed. By using feedback to intelligently select the handling path, the system maintains exception handling completeness while minimizing energy consumption from unnecessary instruction fetching.
Data Source
AI summary
Data processing apparatus comprises a processor configured to execute instructions, the processor having a pipelined instruction fetching unit configured to fetch instructions from memory during a pipeline period of two or more processor clock cycles prior to execution of those instructions by the processor; exception logic configured to respond to a detected processing exception having an exception type selected from a plurality of exception types, by storing a current processor status and diverting program flow to an exception address dependent upon the exception type so as to control the instruction fetching unit to initiate fetching of an exception instruction at the exception address; and an exception cache configured to cache information, for at least one of the exception types, relating to execution of the exception instruction at the exception address corresponding to that exception type and to provide the cached information to the processor in response to detection of an exception of that exception type.