Processor Exclusive Memory Areas for Mode Switching Latency
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Solution Overview
Problem
In computer systems, frequent switching between kernel and user modes leads to increased waiting times and power consumption due to the need for processors to access slow main memory, as data required in one mode is often not stored in the cache, causing unnecessary access to main memory and potential pipeline obstructions.
Innovation Solution
Implementing a computer system with a processor that uses exclusive high-speed memory areas specific to each working mode, allowing smooth data access by connecting the processor with an exclusive memory area based on the current mode through physical or logical switches, and dynamically adjusting the number and size of these areas based on usage frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor accesses main memory to retrieve data after working mode switching, then the required data can be obtained, but the processing speed decreases and waiting time increases
Solution Approach 1:
The cache memory is pre-loaded with data that is likely to be needed after working mode switching. The system predicts which data will be required in the new working mode and loads it into cache memory before the actual access occurs, thereby eliminating waiting time when the processor needs the data.
Solution Approach 2:
Cache memory serves as an intermediary between the processor and main memory. Instead of the processor directly accessing main memory (which is slow), it first accesses the cache memory (which is fast). The cache memory acts as a buffer that stores frequently accessed data, reducing the time the processor spends waiting for data.
2Reliability
If the processor accesses main memory after working mode switching, then the required data can be obtained, but electrical power consumption increases
Solution Approach 1:
Cache memory acts as an intermediary storage layer that reduces the frequency of main memory accesses. Since cache memory is faster and can be accessed with lower power consumption, storing frequently accessed data in cache reduces the overall electrical power consumption of the system while maintaining data availability.
Solution Approach 2:
The system creates a localized high-speed storage area (cache memory) that is optimized for fast access and lower power consumption. Instead of relying on the slower, higher-power main memory for all accesses, the system uses the cache memory for local, frequent accesses, thereby reducing overall power consumption while maintaining data availability.
3Reliability
If the processor waits for data from main memory, then data can be obtained, but pipeline obstruction occurs and power is wasted
Solution Approach 1:
The system pre-loads data into cache memory before the processor needs it, ensuring that data is already available when the processor is ready to access it. This prevents pipeline obstruction by eliminating data waiting time, allowing the processor pipeline to continue executing instructions without interruption.
Solution Approach 2:
Cache memory serves as an intermediary that ensures continuous data supply to the processor pipeline. By storing data in cache memory in advance, the system prevents pipeline stalls that would occur if the processor had to wait for main memory accesses, thereby maintaining high pipeline efficiency and productivity.
Data Source
AI summary
A technology for allowing the smooth acquisition of required data when a processor switches working modes in a computer system is provided. According to one aspect of the present invention, the present invention can provide a computer system including a processor having a plurality of working modes, each having a different privilege level from each other; an exclusive memory area related to a selected one of said plurality of working modes; and a connecting means for connecting said processor with said exclusive memory, depending on said working mode.