Dynamic Processor Execution Rate Regulation for Multiprocessor Failure Recovery

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Solution Overview

Problem

In multiprocessor computer systems, the loss of a single processor can disrupt service levels for businesses, often requiring manual intervention for recovery, and existing redundancy mechanisms may not always ensure continuous operation without human intervention.

Innovation Solution

A method that includes dynamic processor recovery and automatic execution rate regulation, where a disabled processor is replaced or its tasks are reassigned to other processors, and the execution rate of remaining processors is adjusted to maintain system performance without manual intervention, using techniques like processor key-enabled dynamic IP recovery and automatic instruction execution regulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If redundancy switching is implemented to recover from processor failure, then system reliability is improved, but manual intervention is still required and service continuity is not fully ensured

Engineering Contradiction:
Improveprocessor failure recoveryVSAvoidmanual intervention requirement
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The system automatically detects processor failures, identifies spare processors, and executes switching operations without human intervention. The control logic autonomously monitors processor status, triggers recovery procedures, and restores service continuity, eliminating the need for manual operator actions.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

Spare processors are pre-configured and staged in advance within the system architecture. When a processor failure occurs, the pre-positioned spares are immediately activated through automatic switching, eliminating recovery delays that would otherwise require manual intervention.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If processor tasks are redistributed to remaining processors, then system continuity is maintained, but execution rate of individual processors increases causing performance degradation

Engineering Contradiction:
Improvesystem continuityVSAvoidexecution rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system dynamically adjusts execution rate parameters of remaining processors based on their current workload and capacity. When processors assume additional tasks from failed units, their execution rates are automatically modulated to prevent overload and maintain overall system performance within acceptable thresholds.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The processor workload distribution and execution rates are made dynamic rather than static. The system continuously monitors processor performance metrics and automatically rebalances task allocation and execution speeds to adapt to changing system conditions, ensuring optimal performance under varying load scenarios.

Inventive Principle:
Principle #15Dynamics

3Reliability

If system-wide execution rate is maintained after processor failure, then service level is preserved, but energy consumption and processor stress increase

Engineering Contradiction:
Improveservice level maintenanceVSAvoidprocessor energy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system selectively adjusts execution rate parameters based on actual system needs and processor capabilities. Rather than uniformly increasing all processor speeds to maintain service levels, the control logic dynamically modifies parameters for specific processors based on their workload, capacity, and energy efficiency considerations.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7734952B1System and method for maintaining a constant processor service level in a computer
Publication Date: 2010.06.08 UNISYS CORP
  • US7734952B1 patent drawing
  • US7734952B1 patent drawing
  • US7734952B1 patent drawing

AI summary

A method and system for maintaining the execution speed of a multiprocessor computer system includes automatically detecting a change in instruction execution rate in a disabled processor by a threshold amount and determining an amount of change in instruction execution rate to adjust an actual system-level instruction execution rate to approximate a target system-level instruction execution rate. The target system-level execution rate being pre-determined. Thereafter, the method adjusts one or more instruction processor execution rates such that the actual system-level instruction execution rate approximates the target system-level instruction execution rate to overcome the loss of the disabled processor. One embodiment of the invention involves the use of a processor key for licensing of processor resources within the computer system and offers the option of enabling a dynamic processor recovery method as well as an automatic execution rate regulation method.