Out-of-Order Processor Execution Units for Complex Instruction Throughput
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Solution Overview
Problem
Modern processors face challenges in achieving high throughput for all instructions, particularly complex ones like floating-point operations and data moves, which require more execution time and resources, impacting overall performance.
Innovation Solution
The implementation of an out-of-order processor with a packed instruction set architecture that includes execution units capable of handling SIMD instructions, allowing for parallel execution of multiple data elements within a single register, thereby accelerating multimedia and other applications by utilizing the full data bus width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential execution of instructions is used, then simplicity of processor design is maintained, but throughput for complex instructions deteriorates
Solution Approach 1:
The processor implements dynamic instruction scheduling where the out-of-order execution unit selectively reorders instructions based on readiness of operands and availability of execution resources. This dynamic approach allows complex instructions to be executed as soon as their dependencies are satisfied, improving throughput without requiring complete redesign of the processor pipeline.
Solution Approach 2:
The processor divides instruction execution into separate functional units: an out-of-order execution unit for complex instructions and a in-order execution unit for simple instructions. This segmentation allows each unit to be optimized independently, maintaining simplicity for common cases while enabling high throughput for complex operations.
2Productivity
If SIMD instructions with parallel execution are implemented, then execution efficiency of complex instructions is improved, but device complexity increases
Solution Approach 1:
The execution units are designed to handle both scalar and SIMD operations using the same hardware resources. The out-of-order execution unit can dynamically switch between executing single instructions and multiple SIMD instructions based on the instruction stream, eliminating the need for separate dedicated SIMD hardware and reducing overall complexity.
Solution Approach 2:
The processor changes the operational parameters of execution units based on instruction type. When SIMD instructions are detected, the execution units operate in parallel mode with adjusted timing and resource allocation, allowing efficient vector processing without requiring permanently configured separate hardware for each operation type.
3Productivity
If out-of-order execution is implemented, then throughput for complex instructions is improved, but difficulty of detecting and measuring instruction state increases
Solution Approach 1:
The processor introduces intermediary data structures including a reorder buffer and dependency tracking tables that mediate between the out-of-order execution units and the architectural state. These intermediaries maintain the mapping between physical and logical instruction states, allowing accurate tracking of instruction completion and dependency satisfaction without requiring complex direct monitoring of all execution paths.
4Productivity
If full data bus width is utilized for parallel data element execution, then productivity is improved, but use of energy increases
Solution Approach 1:
The processor implements variable-width data path selection where the full data bus width is utilized only when SIMD instructions with multiple data elements are executed. For scalar instructions or when fewer data elements are active, the execution units operate with reduced data path width, avoiding the energy cost of activating unnecessary data buses and execution resources.
Data Source
AI summary
A processor includes a front end to receive an instruction, a decoder to decode the instruction, a core to execute the first instruction, and a retirement unit to retire the first instruction. The core includes logic to execute the first instruction, including logic to repeatedly record a translation lookaside buffer (TLB) until a designated number of records are determined, and flush the TLB after a flush interval.