Processor Fast Translation Table for Complex Instruction Lookup
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Solution Overview
Problem
The process of translating complex instructions into micro-operations in processors is resource-intensive and time-consuming, leading to performance impacts due to the need for decompression and decoding, which can be regarded as instruction traps.
Innovation Solution
A processor employs a fast translation table to directly look up and retrieve micro-operations for specific complex instructions, bypassing decompression and decoding, and uses a combination of hardware components like an instruction translator, register alias table, and microcode device to enable zero-trapping and normal decoding paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If complex instructions are translated using traditional microcode decompression and decoding, then instruction translation completeness is ensured, but translation time and computing resource consumption increase
Solution Approach 1:
The patent segments complex instructions into two categories: frequently executed instructions are pre-translated and stored in a translation cache, while other instructions use traditional microcode translation. This segmentation allows the system to optimize for common cases without completely replacing the traditional translation mechanism, thereby reducing average translation time while maintaining handling capability for all instruction types.
Solution Approach 2:
The patent performs preliminary translation of frequently executed complex instructions during system initialization or idle periods, storing the results in a translation cache. When these instructions are encountered during normal execution, the pre-translated microoperations can be retrieved immediately without undergoing full decompression and decoding, thus reducing translation time for common operations.
2Productivity
If a fast translation table is introduced to speed up instruction translation, then translation speed improves, but storage interface complexity increases
Solution Approach 1:
The patent designs the translation cache to share storage interfaces and control logic with the existing microcode ROM, allowing the same hardware infrastructure to serve both traditional microcode storage and fast translation table functions. This multi-functional approach enables the system to achieve fast translation lookup without completely duplicating storage interfaces, thereby improving translation throughput while limiting the increase in storage interface complexity.
3Reliability
If traditional microcode translation is used for all complex instructions, then translation accuracy is maintained, but processor performance deteriorates due to instruction traps
Solution Approach 1:
The patent applies different translation strategies to different instruction types based on their characteristics and execution frequency. Frequently executed instructions with well-defined translation paths use the fast translation cache to ensure both accuracy and speed, while less common or more complex instructions continue to use traditional microcode translation. This localized optimization maintains translation accuracy for all instructions while improving overall processor performance by reducing traps for common operations.
Data Source
AI summary
A processor with efficient instruction translation is shown, which uses a microcode device that has a first storage device with a micro-operation bit width. The first storage device stores a fast translation table that records micro-operations corresponding to a particular complex instruction. When determining that a received macro instruction is the particular complex instruction, an instruction translator operates a register alias table hardware to enable the microcode device to query the fast translation table to obtain and return the micro-operations corresponding to the particular complex instruction to the register alias table hardware, for running execution units of the processor.