Processor In-Band Fault Injection Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing microprocessor technologies are vulnerable to fault injection attacks, which can cause bit errors in code instructions, leading to unpredictable behavior and potential information extraction from secure electronic circuitry.
Innovation Solution
The integration of error-detection bits into code instructions, monitored by protection circuitry that initiates a responsive action upon detecting errors, including the insertion of error-detection bits at reserved or de-facto reserved locations, and the use of parity or other error-detection schemes to verify bit integrity without modifying the instruction set architecture or affecting execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error-detection bits are inserted into code instructions, then reliability of code execution is improved, but device complexity increases
Solution Approach 1:
The error-detection bits are nested within the existing instruction format by utilizing reserved bits in the instruction word. The protection circuitry is integrated into the existing pipeline architecture, with error detection functionality embedded in the fetch/decode stages. This nesting approach allows error detection capability to be added without significantly increasing external complexity or requiring separate dedicated hardware structures.
Solution Approach 2:
The protection circuitry serves multiple functions: it performs error detection using the error-detection bits, identifies fault-injection attacks, and triggers appropriate responses. The same circuitry that handles normal pipeline operations also monitors for errors, making the system more universal rather than requiring separate dedicated error detection hardware for each function.
2Reliability
If error-detection bits are monitored and responsive actions are initiated, then security against fault injection attacks is improved, but productivity decreases
Solution Approach 1:
When an error or fault-injection attack is detected, the system quickly skips to the next instruction or triggers an immediate response without attempting to recover or continue execution of the compromised instruction. This rushing through of the error handling process minimizes the time lost to security checks and maintains overall execution throughput by avoiding prolonged pauses.
Solution Approach 2:
The system performs partial error detection (monitoring only critical instructions or specific bit positions) rather than exhaustive detection of all possible error conditions. This partial action approach reduces the computational overhead of error monitoring while maintaining adequate security against fault-injection attacks, thereby preserving processor productivity.
3Ease of manufacture
If error-detection bits are inserted at reserved bit locations, then ease of manufacture is improved, but measurement precision of error detection decreases
Solution Approach 1:
Different parts of the instruction word are assigned different qualities: the error-detection bits are placed in reserved bit locations that have specific local characteristics (ignored by the execution unit but monitored by protection circuitry). This local quality differentiation allows the error detection function to operate without interfering with the execution function, maintaining both ease of manufacture and measurement precision.
Data Source
AI summary
An apparatus for protecting a processor includes an input interface and protection circuitry. The input interface is configured to monitor code instructions that are processed by the processor, one or more of which code instructions including one or more error-detection bits. The protection circuitry is configured to detect an error in the program code using the error-detection bits, and to initiate a responsive action in response to detecting the error.