Multi-Core Processor Fault Detection via Instruction Comparison
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Solution Overview
Problem
Conventional technologies fail to detect and correct faults in individual units of processor cores, which can affect processing results and are not addressed by existing multi-core fault detection systems.
Innovation Solution
An apparatus and method that include fetch, decoding, and execution fault control units to detect and correct faults in each processor core by executing the same instruction across multiple cores, comparing results, and canceling faulty instructions to maintain processing integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processor cores are employed to improve processing capability, then productivity is improved, but the complexity of detecting and measuring faults in individual units increases
Solution Approach 1:
The fault detection system is segmented into dedicated control units for each processor core (fetch fault control unit, decoding fault control unit, execution fault control unit). Each control unit independently monitors its corresponding processor core, allowing parallel fault detection without increasing overall system complexity. This segmentation enables the system to handle multiple processor cores while maintaining manageable detection complexity through modular architecture.
2Reliability
If fault detection mechanisms are added to each processor core unit, then reliability is improved, but device complexity increases
Solution Approach 1:
The fault detection functionality is merged with the existing processor core structure by integrating control units directly into the processor architecture. The fetch fault control unit, decoding fault control unit, and execution fault control unit are combined with their respective processor core components, creating a unified system that provides fault detection without adding separate standalone monitoring systems. This merging approach improves reliability while minimizing the increase in device complexity.
Solution Approach 2:
The control units serve multiple functions: they monitor execution results, compare outputs across processor cores, identify faults, and generate appropriate responses. This multi-functionality reduces the need for separate dedicated components for each detection task, thereby improving reliability through comprehensive monitoring while keeping the overall device complexity manageable through versatile, multi-purpose units.
3Measurement precision
If execution results of multiple processor cores are compared to detect faults, then measurement precision is improved, but loss of time increases due to additional comparison operations
Solution Approach 1:
The system executes the same instruction simultaneously across multiple processor cores before performing comparison operations. By preparing and executing instructions in parallel across all processor cores upfront, the system minimizes the time required for fault detection. The comparison operation then simply needs to check results against pre-executed values from other cores, rather than requiring sequential execution and comparison, thus improving measurement precision while reducing the time penalty.
Data Source
AI summary
An apparatus and method for detecting the fault of a processor are disclosed. The apparatus includes a fetch fault control unit, a decoding fault control unit, and an execution fault control unit. The fetch fault control unit detects the fault of each of fetch units of a plurality of processor cores connected to memory. The decoding fault control unit detects the fault of each of decoding units of the plurality of processor cores connected to the memory. The execution fault control unit detects the fault of each of execution units of the plurality of processor cores connected to the memory, executes the same instruction in the plurality of processor cores, determines a processor core where a fault has occurred, and provides notification of the determined processor to the fetch fault control unit and the decoding fault control unit.