Processor Flip-Flop Allocation for Lower Power Data Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Processor circuits consume significant energy due to the power consumption of flip flops, especially in intense data calculations, as they frequently change states, leading to high energy usage across the entire processor.
Innovation Solution
Implementing a data storage module with a combination of multibit flip flop circuits (MBFFs) and single bit flip flop circuits (SBFFs), where MBFFs with lower power consumption per bit are used for data bits that toggle more frequently, and SBFFs with higher power consumption are used for data bits that toggle less frequently, optimizing power usage across the processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flip flops are used to store data in processor circuits, then data storage and processing capability is improved, but power consumption increases significantly
Solution Approach 1:
The patent applies local quality by differentiating between two types of flip-flop circuits with different power consumption characteristics. First flip-flop circuits are designed for high-speed operation with higher power consumption, while second flip-flop circuits are designed for lower power consumption. The system selectively assigns data bits to appropriate flip-flop types based on their toggle frequency characteristics, thereby optimizing the local power consumption properties of different storage locations within the processor.
Solution Approach 2:
The patent changes the power consumption parameter of flip-flop circuits by introducing multiple variants with different operational characteristics. By monitoring the toggle frequency of data bits and dynamically or statically assigning them to flip-flop circuits with appropriate power consumption parameters, the system achieves overall power reduction while maintaining necessary processing performance.
2Productivity
If flip flops frequently change states to perform intense data calculations, then computational performance is improved, but energy expenditure increases
Solution Approach 1:
The patent addresses this contradiction by creating heterogeneous flip-flop regions within the data storage module. High-frequency toggling data bits are assigned to first flip-flop circuits that are optimized for speed, while low-frequency toggling data bits are assigned to second flip-flop circuits optimized for low power consumption. This local differentiation allows the system to achieve high computational performance where needed while minimizing energy loss in less critical operations.
Solution Approach 2:
The system dynamically adapts to the actual usage patterns of data bits by monitoring toggle frequencies and reassigning bits to appropriate flip-flop circuits. This dynamic allocation ensures that energy expenditure is optimized based on actual computational demands, allowing the system to maintain high performance during intensive calculations while reducing energy consumption during lighter workloads.
3Device complexity
If all data bits are stored in the same type of flip flop circuit, then circuit design simplicity is maintained, but power optimization opportunity is lost
Solution Approach 1:
The patent segments the data storage functionality into two distinct types of flip-flop circuits within the same data storage module. This segmentation allows different power consumption strategies to be applied to different data bits based on their toggle frequency characteristics. The first flip-flop circuits handle high-frequency data with higher power consumption, while the second flip-flop circuits handle low-frequency data with reduced power consumption, thereby optimizing overall power usage without significantly complicating the modular design.
Solution Approach 2:
The data storage module maintains universality by being able to store any data bit in either type of flip-flop circuit based on operational requirements. The module can dynamically reassign data bits between different flip-flop types, providing multi-functionality that adapts to varying computational workloads while maintaining a unified interface and control structure.
Data Source
AI summary
Embodiments of the present disclosure pertain to reducing power consumption in a processor circuit. In one embodiment, a processor circuit comprises a plurality of data storage modules. The plurality of data storage modules each include one or more first multibit flip flop circuits having a first power consumption per bit and one or more second flip flop circuits having a second power consumption per bit. The first multibit flip flop circuits may have more bits than the second flip flop circuits. Additionally, the first power consumption per bit may be less than the second power consumption per bit such that power consumption is reduced when the first multibit flip flop circuits are used to store bits that change with a higher frequency than bits stored in the second flip flop circuits.