Processor Flip-Flop Allocation for Lower Switching Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Processor circuits consume significant energy due to the power consumption of flip flops, especially in intense data calculations, as each state change in flip flops results in energy expenditure, and existing methods for optimizing flip-flop grouping and clock gating are not optimal, leading to subpar energy savings.
Innovation Solution
Implementing a data storage module that uses multibit flip flop circuits for data bits that toggle with higher frequency and single bit flip flop circuits for those that toggle less frequently, optimizing power consumption by assigning bits based on their toggling rates and criticality in the processing path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If multibit flip flop circuits are used for frequently changing bits, then power consumption is reduced, but device complexity increases due to heterogeneous flip flop integration
Solution Approach 1:
The data storage module is segmented into multiple banks, where each bank contains a mix of multibit and single-bit flip-flop circuits. This segmentation allows the system to apply different flip-flop types to different bit positions based on their toggling characteristics, reducing overall power consumption while managing complexity through modular organization.
Solution Approach 2:
Different types of flip-flop circuits (multibit vs. single-bit) are selectively applied to different bit positions within the data storage module based on local toggling frequency requirements. Bits that change frequently are assigned to multibit flip-flops for lower power consumption, while less frequently changing bits use single-bit flip-flops, optimizing power efficiency at the local level.
2Use of energy by moving object
If heterogeneous flip flop circuits are integrated in the data storage module, then power consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The data storage module is divided into multiple banks, with each bank containing a standardized mix of multibit and single-bit flip-flop circuits. This segmentation into reusable bank units simplifies manufacturing by allowing standardized modules to be replicated and assembled, reducing the overall manufacturing complexity despite the heterogeneous circuit types.
Solution Approach 2:
The system varies the configuration parameter of flip-flop types (multibit vs. single-bit) across different banks and bit positions based on measured or predicted toggling frequencies. This parameter-based differentiation allows the manufacturing process to optimize power consumption by selecting appropriate flip-flop types for specific applications within the data storage module.
Data Source
Figure 1~2
Figure 3~5
Figure 6~8
AI summary
Embodiments of the present disclosure pertain to reducing power consumption in a processor circuit. In one embodiment, a processor circuit comprises a plurality of data storage modules. The plurality of data storage modules each include one or more first multibit flip flop circuits having a first power consumption per bit and one or more second flip flop circuits having a second power consumption per bit. The first multibit flip flop circuits may have more bits than the second flip flop circuits. Additionally, the first power consumption per bit may be less than the second power consumption per bit such that power consumption is reduced when the first multibit flip flop circuits are used to store bits that change with a higher frequency than bits stored in the second flip flop circuits.