Processor Floating Point Logic with Dynamic Mantissa Exponent Selection
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Solution Overview
Problem
Conventional computer processors are hard-wired to use a fixed floating point number format, limiting flexibility in trade-offs between range and precision, which can be inadequate for various applications such as artificial intelligence and mixed-length format operations.
Innovation Solution
A processor with a flexible floating point format that allows programmable selection of mantissa and exponent bit sizes, enabling variable trade-offs between range and precision, and supporting operations across different formats, including combinations with zero or non-zero sign bits, within a fixed register size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed floating point number format is used in the processor, then the hardware design is simple and deterministic, but the flexibility in trade-offs between range and precision is limited
Solution Approach 1:
The processor dynamically selects between multiple floating point format variants (e.g., IEEE 754, bfloat16, DLFloat) based on the specific data values being processed. The format selection is determined by examining the exponent and mantissa bit patterns of the input operands, allowing the system to adapt the number format to match the actual range and precision requirements of the data, rather than being constrained to a single fixed format.
Solution Approach 2:
The invention changes the parameters of the floating point format (exponent width, mantissa width, bias value) based on the characteristics of the input data. By detecting the actual exponent ranges and precision requirements of the operands, the processor selects format variants with appropriate parameter configurations, enabling optimal trade-offs between range and precision for different computational workloads.
2Adaptability or versatility
If different floating point format variants are supported, then flexibility in operations is improved, but the complexity of floating point logic increases
Solution Approach 1:
The floating point logic is segmented into multiple specialized execution paths, each optimized for a specific format variant. The processor includes separate logic circuits for IEEE 754 format, bfloat16 format, and DLFloat format operations. A format detection mechanism identifies which variant is being used, and the corresponding segmented logic path is activated, allowing multiple formats to be supported without requiring a single complex universal implementation.
Solution Approach 2:
An intermediary format conversion mechanism is introduced to bridge between different floating point format variants. When operands in different formats need to be operated upon, the system automatically converts them to a common intermediate representation, performs the operation, and converts the result back to the appropriate target format. This intermediary approach simplifies the core arithmetic logic while maintaining support for multiple format variants.
3Measurement precision
If a fixed register width is used, then hardware design is simplified, but the ability to represent different precision requirements is constrained
Solution Approach 1:
The fixed-width registers are designed to be universal containers that can hold multiple floating point format variants. The same physical register structure (e.g., 16-bit or 32-bit) is used to store IEEE 754, bfloat16, and DLFloat formats by interpreting the bit patterns according to the detected format type. This multi-functional register design eliminates the need for separate physical registers for each format while maintaining full precision representation capability for all supported variants.
Data Source
AI summary
A processor comprising: a register file comprising a group of operand registers for holding data values, each operand register being a fixed number of bits in length for holding a respective data value of that length; and processing logic comprising floating point logic for performing floating point operations on data values in the register file, the floating point logic is configured to process the fixed number of bits in the respective data value according to a floating point format comprising a set of mantissa bits and a set of exponent bits. The processing logic is operable to select between a plurality of different variants of the floating point format, at least some of the variants having a different size sets of mantissa bits and exponent bits relative to one another.