Multi-Core Processor Control for Floating-Point Power Limiting
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Solution Overview
Problem
Existing multi-core processors face challenges in inhibiting electric-current consumption from exceeding an upper limit when dynamically controlling clock frequency and power supply voltage, leading to increased processor and system costs due to the need for additional power supply pins.
Innovation Solution
A processor with multiple cores and frequency voltage control units that dynamically adjust the issuance frequency of floating-point arithmetic instructions based on the current clock frequency and power supply voltage, preventing excessive power consumption by reducing the issuance frequency when these values increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic voltage and frequency scaling is implemented to control power consumption, then power consumption can be inhibited from exceeding upper limit, but additional power supply pins are required which increases processor cost and package size
Solution Approach 1:
The instruction issuance control unit autonomously adjusts the issuance frequency of floating-point arithmetic instructions based on real-time detection of clock frequency and power supply voltage, eliminating the need for external power supply pins. The core self-regulates its instruction issuance behavior to maintain power consumption within acceptable limits.
Solution Approach 2:
The system dynamically changes the issuance frequency parameter of floating-point arithmetic instructions in response to changes in clock frequency and power supply voltage. By adjusting this operational parameter, the processor controls power consumption without requiring additional physical power supply pins.
2Use of energy by moving object
If issuance frequency of floating-point arithmetic instructions is reduced to control power consumption, then power consumption decreases, but processing performance may be affected
Solution Approach 1:
The instruction issuance control unit dynamically adjusts the issuance frequency based on real-time conditions of clock frequency and power supply voltage. The system adapts its behavior to balance power consumption and processing performance, increasing issuance frequency when conditions permit and reducing it when power limits are approached.
Solution Approach 2:
The system implements feedback control where the instruction issuance control unit detects current clock frequency and power supply voltage, and uses this information to adjust the issuance frequency of floating-point arithmetic instructions. This closed-loop control ensures power consumption remains within limits while maintaining optimal performance.
Data Source
AI summary
A processor includes a plurality of cores each including a floating-point arithmetic unit; a frequency voltage control unit provided corresponding to each of the plurality of cores, the frequency voltage control unit being configured to supply a clock having a variable frequency and a power supply voltage having a variable voltage to the corresponding core; and an instruction issuance control unit provided in each of the plurality of cores, the instruction issuance control unit being configured to control issuance of a floating-point arithmetic instruction to the floating-point arithmetic unit and lower an issuance frequency of floating-point arithmetic instructions to the floating-point arithmetic unit as a current frequency value of the clock is larger than a reference frequency value, or as a current power supply voltage value is larger than a reference power supply voltage value.