Processor Forced Idle State Control via Activity Monitoring

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Solution Overview

Problem

The increasing power requirements and energy consumption of multicore processors pose a significant challenge for energy efficiency, particularly due to software inefficiencies and hardware demands, leading to substantial electricity usage across various computing devices, necessitating innovative power management strategies.

Innovation Solution

Implementing a dynamic power management system that enables and disables forced idle states in processors based on the frequency of triggering events, using integrated voltage regulators and power control units to optimize power usage by refraining from idle state entry during 'noisy' periods and resuming it during 'quiet' periods, thereby enhancing performance and reducing energy consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If forced idle state operation is continuously enabled to reduce power consumption, then energy efficiency is improved, but performance is degraded due to excessive idle state entries during noisy periods

Engineering Contradiction:

Improveenergy consumptionVSAvoidperformance

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent implements dynamic control of forced idle state operation by monitoring triggering event frequency and adjusting idle state entry behavior accordingly. The system transitions between different operational modes (enabling/disabling forced idle) based on real-time conditions, optimizing the balance between power consumption and performance.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system employs feedback mechanisms by monitoring triggering events (interrupts, cache snoops) and using this information to control forced idle state operation. The power controller continuously assesses system activity levels and adjusts idle state entry decisions based on observed patterns, creating a closed-loop control system.

Inventive Principle:

Principle #23Feedback

2Productivity

If forced idle state entry is prevented during noisy periods to maintain performance, then performance is preserved, but energy consumption increases

Engineering Contradiction:

ImproveperformanceVSAvoidenergy consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The system applies partial action by selectively enabling forced idle state operation only during quiet periods when it is beneficial, rather than continuously enabling or disabling it. This partial application of forced idle states optimizes energy consumption without unnecessarily sacrificing performance during noisy periods.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The system changes operational parameters (forced idle state enable/disable status) based on observed system conditions. By monitoring triggering event frequency and adjusting the forced idle state parameter accordingly, the system adapts to varying workload characteristics and optimizes the energy-performance tradeoff.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If the processor operates at higher performance levels to meet workload demands, then productivity is improved, but power requirements and thermal output increase

Engineering Contradiction:

Improveprocessing throughputVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The system implements periodic forced idle state operation during quiet periods, creating regular cycles of high-performance and low-power states. This periodic action allows the processor to operate at higher performance levels when needed while periodically reducing power consumption and thermal output through forced idle states.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS10324519B2Controlling forced idle state operation in a processor

Publication Date: 2019.06.18 INTEL CORP

AI summary

In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.