Processor Frequency Control via Configurable Peak Limits
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Solution Overview
Problem
The increasing power requirements and variability in processor performance across nodes in computing systems lead to energy inefficiencies and potential software failures, particularly due to opportunistic turbo mode operations exceeding power and thermal constraints.
Innovation Solution
A configurable peak performance limit control mechanism that dynamically limits processor frequency, allowing for turbo mode performance without exceeding power delivery constraints, by using a power control unit to manage voltage and frequency across multiple cores independently, and setting clip values for per-core turbo frequencies based on workload characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If opportunistic turbo mode operation is enabled to increase processor clock frequency, then processor performance is improved, but performance variability across nodes increases and determinism is lost
Solution Approach 1:
The patent implements dynamic frequency scaling with multiple operating frequency levels that can be adjusted in real-time based on workload characteristics and power availability. The processor transitions between different frequency states (including turbo mode and reduced frequency modes) dynamically, allowing optimization of both performance and determinism depending on operational conditions.
Solution Approach 2:
The system changes the operating frequency parameter based on detected workload characteristics. When workloads are detected to be deterministic or time-critical, the system reduces the maximum operating frequency to ensure determinism. When workloads are non-critical, the system allows higher frequencies for improved performance.
2Productivity
If processor clock frequency is increased to maximize performance, then processing speed is improved, but power consumption exceeds delivery constraints
Solution Approach 1:
The patent implements dynamic frequency scaling with multiple operating frequency levels that can be adjusted in real-time based on workload characteristics and power availability. The processor transitions between different frequency states (including turbo mode and reduced frequency modes) dynamically, allowing optimization of both performance and power consumption depending on operational conditions.
Solution Approach 2:
The system continuously monitors power consumption, thermal conditions, and workload characteristics, then adjusts the operating frequency accordingly. Power management controllers and thermal sensors provide feedback to the frequency management logic, which adjusts clock frequencies to maintain operation within power and thermal constraints while maximizing performance when possible.
3Reliability
If turbo mode operation is disabled to ensure deterministic performance, then performance determinism is improved, but overall processor performance is significantly reduced
Solution Approach 1:
The patent implements dynamic frequency scaling with multiple operating frequency levels that can be adjusted in real-time based on workload characteristics and power availability. The processor transitions between different frequency states (including turbo mode and reduced frequency modes) dynamically, allowing optimization of both performance and determinism depending on operational conditions.
Solution Approach 2:
The system changes the maximum operating frequency parameter based on detected workload characteristics. When workloads are detected to be deterministic or time-critical, the system reduces the maximum operating frequency to ensure determinism. When workloads are non-critical, the system allows higher frequencies for improved performance, effectively eliminating the need to completely disable turbo mode.
Data Source
AI summary
In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.


