Processor Frequency Switching for Fault Detection Power Balance
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Solution Overview
Problem
Existing fault detection methods in computer systems, particularly in the field of intelligent driving, face challenges in balancing fault detection speed and power consumption, with current technologies affecting real-time performance and power efficiency due to inadequate frequency adjustment of processors during fault detection processes.
Innovation Solution
A method and apparatus that adjust the running frequency of processors based on the type of test patterns, such as computing-intensive or memory-intensive, to optimize fault detection speed and power consumption, incorporating dynamic voltage and frequency scaling (DVFS) and context switching to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor running frequency is increased to improve fault detection speed, then the fault detection speed is improved, but the power consumption increases
Solution Approach 1:
The patent applies dynamic voltage and frequency scaling (DVFS) to adjust the processor running frequency dynamically based on the test pattern type. Computing-intensive test patterns are executed at higher frequencies to improve detection speed, while memory-intensive test patterns are executed at lower frequencies to reduce power consumption. This dynamic adjustment resolves the contradiction between detection speed and power consumption by adapting the frequency to the specific computational characteristics of each test pattern.
Solution Approach 2:
The patent changes the operating parameters (frequency and voltage) of the processor based on the characteristics of the test pattern. By identifying whether a test pattern is computing-intensive or memory-intensive, the system adjusts the frequency parameter accordingly, thereby optimizing the balance between detection speed and power consumption for different types of fault detection tasks.
2Use of energy by moving object
If the processor running frequency is decreased to reduce power consumption, then the power consumption is reduced, but the fault detection speed decreases
Solution Approach 1:
The system dynamically adjusts the processor frequency based on the test pattern type rather than using a fixed low frequency. For memory-intensive test patterns, lower frequencies are used to reduce power consumption, while for computing-intensive patterns, higher frequencies are applied to maintain detection speed. This dynamic approach resolves the contradiction by selectively reducing frequency only when appropriate.
Solution Approach 2:
The patent implements parameter changes by adjusting the frequency and voltage settings according to the computational characteristics of each test pattern. This allows the system to optimize power consumption for memory-intensive operations while maintaining sufficient speed for computing-intensive operations, thereby resolving the trade-off between power consumption and detection speed.
3Speed
If a fixed high frequency is used for fault detection, then the fault detection speed is improved, but the power consumption increases and real-time performance of service layer tasks deteriorates
Solution Approach 1:
The patent implements dynamic frequency adjustment that allows the processor to operate at high frequencies only when executing computing-intensive test patterns that require fast detection. For memory-intensive patterns and during service layer task execution, the frequency is reduced, thereby maintaining fault detection speed when needed while preserving real-time performance of service tasks during normal operation.
Solution Approach 2:
The system employs periodic context switching between fault detection tasks and service layer tasks, with frequency adjustments applied periodically based on the current task type. This periodic action ensures that high frequency is applied only during fault detection when necessary, while service layer tasks can execute at lower frequencies to maintain real-time performance, thus resolving the contradiction between detection speed and service task productivity.
Data Source
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Figure 2(b)
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AI summary
A fault detection method and apparatus, and an intelligent driving device are disclosed. The method includes: obtaining information about a first test pattern, where the first test pattern is a to-be-run test pattern, and the first test pattern is used to detect a fault of an integrated circuit; and adjusting, to a target frequency based on the first test pattern, a running frequency of a processor configured to run the first test pattern, so that when the processor runs the first test pattern at the target frequency, a running speed of the first test pattern can be increased or power consumption required for running the first test pattern can be reduced. The technical solutions of this application may be applied to the intelligent driving device, to adjust a running frequency of a processor based on an STL test pattern, thereby achieving a balance between a fault detection speed and required power consumption.