Processor Frequency Selection Under Real-Time Supply Voltage Drops
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Solution Overview
Problem
The rapid change in load current causes a significant voltage drop in processor supply voltage due to parasitic impedance, leading to operational issues, which existing methods like increasing decoupling capacitors or reducing operating frequency either increase manufacturing costs, power consumption, or affect performance.
Innovation Solution
A processor with a detection circuit to real-time monitor supply voltage and select from multiple clock signals to adjust operating frequency, ensuring optimal performance without excessive frequency changes or increased power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the supply voltage of the processor is increased to provide sufficient voltage drop buffer, then the processor can maintain stable operation under load changes, but the power consumption of the chip increases
Solution Approach 1:
The patent implements dynamic frequency adjustment by selecting from multiple clock signals based on detected supply voltage levels. The operating frequency is dynamically changed according to real-time voltage conditions, allowing the processor to maintain stability without requiring a permanently elevated supply voltage that would increase power consumption.
Solution Approach 2:
The patent changes the operating frequency parameter in response to supply voltage variations. By adjusting the frequency parameter dynamically, the system compensates for voltage drops without increasing the supply voltage level, thereby avoiding increased power consumption while maintaining operational stability.
2Reliability
If the operating frequency of the processor is reduced to avoid voltage drop issues, then the processor can operate stably under varying loads, but the performance of the processor decreases
Solution Approach 1:
The patent implements dynamic frequency selection based on real-time supply voltage detection. When voltage is sufficient, the processor operates at higher frequencies for optimal performance. When voltage drops are detected, the frequency is reduced only to the extent necessary to maintain stability, rather than permanently reducing performance.
Solution Approach 2:
The patent uses a detection circuit to monitor supply voltage levels and provides feedback for adjusting the operating frequency. This closed-loop feedback mechanism ensures that frequency adjustments are made only when necessary to maintain stability, preserving maximum performance during normal operating conditions.
3Reliability
If the area of the decoupling capacitor inside the chip is increased to prevent voltage drop, then the processor can maintain stable operation, but the manufacturing cost of the chip increases
Solution Approach 1:
The patent replaces the passive electrical solution of larger decoupling capacitors with an active control system consisting of a detection circuit and multiplexer. This substitution achieves voltage stability through dynamic frequency adjustment rather than through increased capacitive storage, avoiding the need for larger, more expensive capacitor components.
Solution Approach 2:
The patent uses parameter changes (frequency adjustment) to achieve voltage stability instead of changing the physical characteristics of passive components like capacitor size. This approach maintains stability without increasing the area or cost of decoupling capacitors.
Data Source
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AI summary
The present invention provides a processor (100) including a core circuit (110), clock signal generation circuits (130_1 - 130_4), a multiplexer (120) and a detection circuit (112) is disclosed. The core circuit (110) is supplied by a supply voltage. The clock signal generation circuits (130_1 - 130_4) are configured to generate clock signals with different frequencies, respectively, wherein a number of the clock signals is equal to or greater than three. The multiplexer (120) is configured to receive the clock signals, and to select one of the clock signals to serve as an output clock signal according to a control signal, wherein the core circuit (110) uses the output clock signal to serve as an operating clock. The detection circuit (112) is configured to detect a level of the supply voltage received by the core circuit (110) in a real-time manner, to generate the control signal.