Processor Graph Flow Unit for Accelerating Calculation
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Solution Overview
Problem
Current superscalar CPU architectures face challenges in scaling performance due to increased complexity and energy consumption, with existing graph flow accelerators experiencing communication delays and limited parallelism, leading to reduced efficiency and performance.
Innovation Solution
Incorporating a hardware graph flow unit within the processor core, allowing direct communication and concurrent execution with general-purpose operation units, and extending the instruction set with graph calculation control instructions to accelerate graph calculations without relying on message channels, thereby reducing communication delays and enhancing parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a graph flow accelerator is used as an independent system with message channels or shared memory for communication, then graph calculation capability is improved, but communication delay increases and system complexity increases
Solution Approach 1:
The patent merges the graph flow accelerator with the superscalar processor into a unified hybrid architecture. The graph flow accelerator is integrated within the processor core, sharing resources such as caches and communication buses, eliminating the need for separate message channels or shared memory interfaces, thereby reducing communication delay while maintaining enhanced graph calculation capability
2Productivity
If a graph flow accelerator is used as an independent system, then graph calculation capability is improved, but device complexity increases
Solution Approach 1:
The patent combines the graph flow accelerator and superscalar processor into a single integrated system, sharing common resources including instruction and data caches, communication buses, and control logic. This integration reduces the number of independent components and interfaces, thereby reducing overall system complexity while preserving graph acceleration functionality
Solution Approach 2:
The hybrid architecture enables the processor to dynamically switch between superscalar execution mode for general-purpose tasks and graph flow execution mode for graph-intensive workloads. This multi-functionality allows a single integrated system to handle diverse computational requirements, reducing the need for separate specialized systems
3Productivity
If superscalar CPU architecture is used to improve throughput, then processing performance is improved, but energy consumption increases
Solution Approach 1:
The patent implements a dynamic hybrid architecture that can switch between superscalar and graph flow execution modes based on workload characteristics. For graph-intensive tasks, the system transitions to graph flow mode which achieves higher throughput with lower energy consumption by exploiting data-level parallelism and reducing dependency checking, thereby improving energy efficiency while maintaining high performance
Data Source
AI summary
This application discloses a processor, a processing method, and a related device. The processor includes a processor core. The processor core includes an instruction dispatching unit and a graph flow unit and at least one general-purpose operation unit that are connected to the instruction dispatching unit. The instruction dispatching unit is configured to: allocate a general-purpose calculation instruction in a decoded to-be-executed instruction to the at least one general-purpose calculation unit, and allocate a graph calculation control instruction in the decoded to-be-executed instruction to the graph calculation unit, where the general-purpose calculation instruction is used to instruct to execute a general-purpose calculation task, and the graph calculation control instruction is used to instruct to execute a graph calculation task. The at least one general-purpose operation unit is configured to execute the general-purpose calculation instruction. The graph flow unit is configured to execute the graph calculation control instruction.