Processor Hardware Resource Access Control via Domain Gateways

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Solution Overview

Problem

Conventional multiprocessor architectures lack flexible protection of hardware resources, leading to unwanted interference between processors, which can cause harmful or fatal operational issues due to the lack of protection for memory devices, DMA channels, and GPIO pins.

Innovation Solution

A system and method that assign hardware resources, including DMA channels and GPIO pins, to specific processor domains at boot time using processor identifiers or domain identifiers, ensuring exclusive access and preventing unauthorized interference through gateway protection circuits and memory protection mechanisms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple DMA channels are shared as a common resource, then hardware resource utilization is improved, but system reliability deteriorates due to unauthorized access and interference between processors

Engineering Contradiction:
Improvehardware resource utilizationVSAvoidsystem reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the shared DMA channel resource into processor-specific domains by assigning unique domain identifiers to each processor. The gateway circuitry then segments access control by checking domain identifiers, allowing each processor to use DMA channels exclusively within its assigned domain while preventing unauthorized access from other processors.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If GPIO pins are not protected, then ease of operation is improved, but system reliability deteriorates due to unauthorized interference with hardware resources

Engineering Contradiction:
Improveaccess to GPIO pinsVSAvoidprotection against unauthorized interference
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent introduces gateway circuitry as an intermediary between processors and GPIO pins. This gateway circuitry mediates access control by checking domain identifiers of requesting processors against assigned permissions, allowing authorized processors to access GPIO pins while blocking unauthorized access, thus maintaining both ease of operation for legitimate users and protection against interference.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If hardware resources are not assigned to specific processor domains, then device complexity is reduced, but harmful factors increase due to runaway processor interference

Engineering Contradiction:
Improvehardware resource assignment mechanismVSAvoidunwanted interference from runaway processors
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent implements preliminary action by assigning domain identifiers to processors and configuring gateway circuitry with these identifiers before processors begin accessing hardware resources. This pre-configuration establishes protection mechanisms in advance, so that when processors operate, the gateway circuitry can immediately enforce domain-based access control to prevent harmful interference from runaway or unauthorized processors.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11755785B2System and method of limiting access of processors to hardware resources
Publication Date: 2023.09.12 NXP USA INC
  • US11755785B2 patent drawing
  • US11755785B2 patent drawing
  • US11755785B2 patent drawing

AI summary

A processing system including processors, peripheral slots, hardware resources, and gateway circuitry. Each processor is assigned a corresponding identifier. The peripheral slots are located within an addressable peripheral space. Each hardware resource is placed into a corresponding peripheral slot, including at least one direct memory access (DMA) device supporting at least one DMA channel and at least one general-purpose input/output (GPIO) pin. Memory protection and gateway circuitry is programmed to control access of the hardware resources only by a processor that provides a matching identifier. The memories along with hardware resources are protected against unauthorized accesses to isolate applications executed on each processor within a multicore system and hence support freedom of interference.