Processor Hash Instruction for Secure SM3 Execution

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing technologies require multiple ISA instructions to implement Hash cryptographic algorithms, leading to poor data security due to exposure of intermediate data.

Innovation Solution

A processor with a single Hash cryptographic instruction that processes input messages using the SM3 algorithm, where intermediate data is protected within the processor's internal storage, preventing external access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple ISA instructions are used to implement Hash cryptographic algorithm, then the algorithm can be executed, but intermediate data is exposed leading to poor data security

Engineering Contradiction:

Improvedata securityVSAvoidinstruction complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple ISA instructions into a single unified Hash cryptographic instruction that performs the entire SM3 algorithm execution. This merging approach consolidates the cryptographic operations and intermediate data handling within a single instruction boundary, preventing intermediate data exposure while maintaining algorithm functionality.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements a nested structure where the Hash cryptographic instruction contains an internal storage space that is nested within the processor architecture. This internal storage space holds intermediate data during algorithm execution, creating a protected nested environment that isolates sensitive intermediate values from external access while the instruction executes.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Reliability

If intermediate data is stored in internal storage space of processor, then data security is improved, but storage space is consumed

Engineering Contradiction:

Improvedata securityVSAvoidinternal storage space

Core Design Contradiction:

ReliabilityVSVolume of stationary object

Solution Approach 1:

The patent applies local quality by creating a specialized internal storage space with different security properties than general-purpose memory. This dedicated storage area is specifically designed to hold intermediate cryptographic data with restricted access permissions, providing localized security enhancement without converting the entire processor storage architecture into a secure environment.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent extracts intermediate data from the general memory system and places it into a separate internal storage space within the processor. This extraction isolates sensitive intermediate values from the broader memory architecture, limiting their exposure scope while maintaining necessary processor functionality.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS12212655B2Processor with a hash cryptographic algorithm and data processing thereof

Publication Date: 2025.01.28 VIA ALLIANCE SEMICON CO LTD

AI summary

A processor with a Hash cryptographic algorithm and a data processing method are shown. In response to one single Hash cryptographic instruction of an instruction set architecture, the processor reads a first storage space within a system memory to obtain an input message of a limited length, and processes the input message in accordance with the Hash cryptographic algorithm to generate a final Hash value of a specific length.