Processor Identifier Bus Mechanism for Access Control
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Solution Overview
Problem
Existing compartmentalized devices with multiple processors lack a mechanism for each processor to obtain its compartment identifier, leading to limitations in access control and resource sharing.
Innovation Solution
Incorporating a second circuit associated with each processor that provides its identifier on the bus during the address phase of each access, and a first circuit in peripherals that stores and returns the identifier during the data phase of read accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a compartmentalized device with multiple processors is used, then access control to peripherals is improved, but processors cannot obtain their compartment identifier
Solution Approach 1:
The patent introduces a first circuit in the peripheral device that acts as an intermediary. This circuit receives the processor identifier from the second circuit during the address phase, stores it temporarily, and returns it to the processor during the data phase. This intermediary mechanism enables the processor to obtain its identifier without disrupting the existing compartmentalized access control architecture.
Solution Approach 2:
The first circuit performs preliminary action by storing the processor identifier during the address phase, before the data phase occurs. This advance storage allows the identifier to be readily available when the processor requests it during the data phase, enabling efficient identifier retrieval without adding significant overhead to the access control process.
2Loss of information
If a second circuit provides identifier on the bus during address phase, then processor identifier availability is improved, but bus communication complexity increases
Solution Approach 1:
The first circuit is designed with multi-functionality, serving both as a regular peripheral component and as an identifier storage/return mechanism. During normal operations, it functions as a standard peripheral, while during identifier retrieval operations, it activates its additional function of storing and returning the processor identifier. This universality avoids adding dedicated complex infrastructure solely for identifier management.
Solution Approach 2:
The patent merges the identifier management function with the existing bus communication infrastructure. The second circuit integrates the identifier provision into the standard bus protocol, and the first circuit combines identifier storage with regular peripheral operations. This merging approach allows identifier communication to occur through existing channels rather than requiring separate dedicated communication paths.
3Loss of information
If read access stores identifier during address phase and returns it during data phase, then identifier retrieval is enabled, but access time increases
Solution Approach 1:
The identifier retrieval process maintains continuity by utilizing the existing two-phase bus communication structure. The first circuit continuously operates during both phases: storing the identifier during the address phase (which would otherwise be idle for this purpose) and returning it during the data phase. This approach extracts useful action from existing time slots without requiring additional time beyond the standard access cycle.
Data Source
AI summary
The present description concerns a device comprising a bus, peripherals coupled to the bus, the peripherals comprising a first circuit, processors coupled to the bus and initiating accesses to the peripherals, each comprising an address phase followed by a data phase, and for each processor, a second circuit delivering an identifier of the processor over the bus during the address phase of each access initiated by the processor. For each read access to the first circuit initiated by one of the processors, the first circuit stores the identifier present over the bus during the address phase of the access, and then delivers the identifier stored over the bus during the data phase of the access.