Processor Idle Signal Controls Memory Data Retention
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Solution Overview
Problem
Existing methods for reducing power consumption in mobile devices by placing RAM in data retention mode are complex and costly, requiring hardware or software modifications, which complicates the design and increases development costs.
Innovation Solution
A processing system with a processor that generates an idle mode signal to directly control a memory's data retention mode, allowing the RAM to enter a low power state without code modifications, and enabling tunable wake-up latencies based on selected idle modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If complex external hardware or complicated software is used to optimize power consumption through data retention mode, then power consumption is reduced, but device complexity and development cost increase
Solution Approach 1:
The patent merges the power management function directly into the processor by integrating a data retention control logic unit within the processor architecture. This allows the processor to autonomously control the memory's data retention mode without requiring separate external hardware or complex software, thereby reducing device complexity while maintaining power consumption optimization.
Solution Approach 2:
The processor performs self-service power management by having its own control logic that automatically determines when to place memory in data retention mode based on its operational state. This eliminates the need for external control mechanisms and simplifies the overall system architecture while achieving effective power optimization.
2Use of energy by moving object
If RAM is placed in data retention mode to reduce power consumption, then power consumption is reduced, but software compatibility and ease of implementation deteriorate due to required code modifications
Solution Approach 1:
The processor autonomously manages memory power states through integrated control logic that monitors processor state and automatically generates control signals for the memory. This self-service mechanism eliminates the need for software code modifications while achieving effective power management, as the control is handled at the hardware level within the processor itself.
3Loss of energy
If supply voltage to memory is reduced to decrease current leakage, then current leakage is reduced, but data retention capability may be compromised
Solution Approach 1:
The patent utilizes the memory's data retention mode capability, which is a specific operational parameter state that allows the memory to retain data at reduced supply voltages. By controlling the memory to enter this specific parameter state through the integrated control logic, the system achieves reduced current leakage while maintaining data integrity, as the memory is designed to preserve data in this low-power state.
Data Source
AI summary
A processing system includes a processor (20) having an idle mode node for generating an idle mode signal indicating whether the processor is in an idle mode and a memory (22) having a data retention node for receiving a data retention mode signal. The memory includes circuitry for placing the memory in a low power state responsive to the data retention mode signal. The idle mode signal drives the data retention node, such that the memory is placed in the low power state when the processor is in idle mode.