Processor Illegal Instruction Exception Handling

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Solution Overview

Problem

Microprocessors face challenges in handling illegal instructions, particularly when they encounter instructions that do not comply with the defined instruction set architecture, as existing solutions struggle to manage exception state effectively, especially when supporting multiple instruction encodings.

Innovation Solution

The processor is configured to convert instructions to a uniform format early in the pipeline while preserving the original compressed instruction information, allowing for accurate exception handling by generating exceptions using the original compressed form, ensuring compliance with architecturally-defined expectations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the processor converts instructions to a uniform format early in the pipeline, then the processor design is simplified and code density is improved, but the original compressed instruction information is lost making exception handling complicated

Engineering Contradiction:
Improveprocessor design complexityVSAvoidoriginal compressed instruction information
Core Design Contradiction:
Device complexityVSLoss of information

Solution Approach 1:

The instruction processing pipeline is segmented into multiple stages: a conversion stage that transforms compressed instructions to uniform format, and a preservation stage that maintains copies of original compressed instructions. This segmentation allows the system to simultaneously achieve simplified processing (through conversion) and information preservation (through copying), resolving the contradiction between device complexity reduction and information loss prevention.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different parts of the instruction processing system are assigned different qualities: the main execution pipeline receives converted uniform-format instructions for simplified processing, while exception handling units receive preserved original compressed instructions for accurate exception generation. This local differentiation allows each component to operate with the appropriate instruction format for its specific function.

Inventive Principle:
Principle #3Local quality

2Reliability

If the processor preserves original compressed instruction information for exception handling, then accurate exception handling is achieved, but the processor design becomes more complicated

Engineering Contradiction:
Improveexception handling accuracyVSAvoidprocessor design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The processor performs preliminary action by converting compressed instructions to uniform format early in the pipeline before execution. This advance conversion simplifies the main processing path while allowing the system to later use the pre-converted uniform format instructions for exception handling, reducing the need for complex preservation mechanisms and thereby reducing overall device complexity while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If the processor uses multiple instruction encodings (16-bit and 32-bit), then code density is improved, but managing exception state becomes more complicated

Engineering Contradiction:
Improvecode densityVSAvoidexception state management complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The processor applies parameter changes by transforming the instruction format parameter from variable-length (16-bit or 32-bit) to a fixed uniform format (32-bit). This parameter transformation simplifies exception state management because the uniform format provides consistent instruction boundaries and structures, making it easier to identify and handle illegal instructions regardless of their original encoding size, thereby reducing the complexity of managing exception state while preserving the benefits of compressed instruction encoding.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11086631B2Illegal instruction exception handling
Publication Date: 2021.08.10 CADENCE DESIGN SYST INC
  • US11086631B2 patent drawing
  • US11086631B2 patent drawing
  • US11086631B2 patent drawing

AI summary

Techniques are disclosed relating to the handling of exceptions generated by illegal instructions in a processor. In an embodiment, a processor may be configured to fetch instructions defined according to an instruction set architecture (ISA). The ISA may include a set of uncompressed instructions and a set of compressed instructions. The processor may further be configured to, upon detecting a given one of the set of compressed instructions, cause a copy of the given compressed instruction to be saved and convert the given compressed instruction to a corresponding given uncompressed instruction. The processor may also be configured to detect that the given uncompressed instruction is illegal and was converted from the given compressed instruction, and based at least in part on these, cause an illegal instruction exception to be generated using the copy of the given compressed instruction.